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In this paper, we report a graphene based nanoporous silicon immunosensor for detection of aflatoxin B1 (AFB1).The binding density of antibodies on graphene coated nanoporous silicon is estimated by standard optical density method and compared with the conventionally silanized nanoporous silicon substrate. It is observed that the binding capability of antibody on graphene based substrate is nearly 1.5 times higher than that on the conventional substrates. With the application of different concentration of AFB1 in the range of 1 fg/ml-1 pg/ml the impedance response of this biosensor is experimentally verified. It is observed that the impedance decreases with frequency as reported for only nanoporous silicon substrate. However the sensitivity exhibits the presence of both minima and maxima with frequency unlike the previous report. Further the maximum value of sensitivity for AFB1 detection is 1.3 times more than that compared to the ordinary silicon substrate. Thus graphene coated nanoporous silicon substrate is capable of detecting toxin even in sub-femtomolar concentration with distinct frequency characteristics. [ABSTRACT FROM AUTHOR]

This paper reports the design and fabrication of electrode microtraps for single cell trapping and impedance measurement. In this work, the microtrap electrodes of parallel and elliptical geometry have been fabricated by electroplating of gold electrodes of optimum thickness. This has enabled the formation of electrode traps without requiring any precision alignment between separate insulating traps like PDMS and the bottom gold electrodes. Further the improved uniformity of the electric field between the trapping electrodes as observed from COVENTORWARE simulation significantly reduces the effect of cell position inside the microwell on the electrical measurement unlike previous reports. This makes it possible to directly extract the equivalent cell parameters from the electrical measurement without introducing any correction factor corresponding to cell position. We have performed impedance spectroscopy with both the microwell electrode structures with single HeLa cell at two different positions of trapping. It has been observed that there is almost no change in the extracted values of cell resistance and capacitance for different positions within parallel electrodes and there is only 0.7 % and 0.85 % change in cell resistance and capacitance for the two positions within elliptical electrodes. Thus these microwell electrode structures can be used as an improved and a more convenient platform for single cell electrical characterization. [ABSTRACT FROM AUTHOR]

The paper focuses on the design of a CMOS analog ASIC for temperature-drift compensation of a high sensitivity piezoresistive micro-machined porous silicon pressure sensor to avoid analog-to-digital conversion, limit chip area and reduce power consumption. For implementing the compensation circuitry, multilayered perceptron (MLP) based artificial neural network (ANN) with inverse delayed function model of neuron has been optimized. The temperature drift compensation CMOS ASIC has been implemented to make porous silicon pressure sensor an excellent SMART porous silicon pressure sensor. Using the compensation circuit, the error in temperature-drift has been minimized from 93% to about 0.5% as compared to 3% using conventional neuron model in the temperature range of 25-80°C. The entire circuit has been designed using 0.35 μm AMS technology model and simulated using mentor graphics ELDO Simulator. [ABSTRACT FROM AUTHOR]

In this paper, an improved voltage controlled oscillator scheme with temperature compensated frequency, a wide linear range, low phase noise and low power dissipation is presented for application in transmitting signals of gas sensors from mines using RF communication. The basic unit of the oscillator is a ring based differential amplifier incorporating temperature compensated voltage dependent PMOS capacitors and standard PMOS triode connected load with temperature compensated biasing scheme. The increased nonlinearity in the presence of PMOS capaciors is reduced to 0.001% using a digitally programmable neural architecture which is simulated in the mixed signal domain of SYNOPSYS. Additionally, the temperature compensated PMOS capacitor improves the sensitivity of the VCO and the standard temperature compensated biasing scheme of the PMOS triode connected load reduces the drift in amplitude with temperature variation. The PMOS varactor lowers the phase noise of the VCO compared to parasitic capacitors without increasing the power dissipation. The entire VCO is designed using 0.18 μm typical technology of TSMC with 1.8 V power supply. The tuning range of the VCO is 0.3-1.7 V, maximum frequency is 1 GHz with a linear change of around 750 MHz, temperature sensitivity and power consumption are around 50 ppm/°C and 2 mW respectively. The phase noise is obtained to be around −123dBc/Hz at 1 MHz offset frequency. [ABSTRACT FROM AUTHOR]