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In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point P 1 dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P 1 dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters. [ABSTRACT FROM AUTHOR]

This Mixed Signal Letter presents a proposal of four-quadrant linear-assisted DC/DC voltage regulator. In this topology, a class-AB linear voltage amplifier assists a four-quadrant switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e., high efficiency, inherent in switching converters, and low output ripple and fast reaction to the load changes that are characteristics of linear regulators. In order to reduce the power dissipation in the linear regulator, it is considered as an assisting circuit for providing just a small fraction of the total load current. Furthermore, this stage provides the required clock signal for the switching counterpart, obtaining a compact topology thanks to the reduction of the complexity in the design of the control scheme for the switching converter. In fact, the proposed topology can be addressed to on-chip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance power-supply modulators for envelope tracking techniques in power amplifiers. The implementation and results indicate that the proposed four-quadrant linear-assisted DC/DC regulator can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives. [ABSTRACT FROM AUTHOR]

A new ultra-wideband common gate low noise amplifier (LNA) for 3-6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5-3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than −11 and −14 dB, respectively, over the entire frequency band of 3-5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, −15 and −9 dB for the frequency band of 5-6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and −1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply. [ABSTRACT FROM AUTHOR]