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Having a system that can take an image of a natural scene and accurately classify the plants in it is of undeniable importance. However, the complexities of dealing with natural scene images and the vast diversity of plants in the wild make designing such a classifier a challenging task. Deep Learning (DL) lends itself as viable solution to tackle such complex problem. However, advanced in DL architectures and software (including DL frameworks) come with a high cost in terms of energy consumption especially when employing Graphics Processing Units (GPU). As data expands rapidly, the need to create energy-aware models increases in order to reduce energy consumption and move towards "Greener AI". Since the problem of designing energy-aware architectures for plant classification has not been studied significantly in the literature, our work comes to start bridging this gap by focusing not only on the models' performance, but also on their energy usage on both CPU and GPU platforms. We consider different state-of-the-art Convolutional Neural Networks (CNN) architectures and train them on two famous challenging plants datasets: iNaturalist and Herbarium. Our experiments are meant to highlight the trade-off between accuracy and energy consumption. For examples, the results show that while GPU-bound models can be about 40% faster in terms of training time than simple models running on CPU, the latter's energy consumption is only two thirds of the former. We hope that such findings will encourage the community to reduce its reliance on accuracy measures to compare different architectures and start taking other factors into account such as power consumption, simplicity, etc. [ABSTRACT FROM AUTHOR]

The extensive amount of data and contents generated today will require a paradigm shift in processing and management techniques for these data. One of the important data processing operations is the data sorting. Using multiple passes in external merge sort has a great influence on speeding up the sorting of extremely large data files. Since in large files, the swapping time is dominant in many applications, algorithms that minimize the swapping operations are normally superior to those which only focus on CPU time optimizations. In sorting extremely large files, external algorithms, such as the merge sort, are normally used. It is shown that using multiple passes over the data set, as proposed in our algorithm, has resulted in a great improvement in the number of swaps, thus, reducing the overall sorting time. Moreover, the proposed technique is suitable to be used with the emerging parallelization techniques such as GPUs. The reported results show the superiority of the proposed technique for "CPU only" and hybrid CPU–GPU implementations. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

The cache memory has a direct effect on the performance of a computer system. Instructions and data are fetched from a fast cache instead of a slow memory to save hundreds of cycles. Reducing the cache miss ratio will definitely improve the execution time of an application. In this work, we propose cache memory designs that reduce the number of conflict misses significantly. The proposed designs reduce the conflict misses in the last level multi-way set associative cache. Each set is divided into a group of subsets: the first is referred to as the exclusive subset, and the rest are the shared subsets. The exclusive is configured as a traditional cache where each block is mapped to the set whose index matches the block index. In addition to their standard cache indexing role, the shared subsets are configured to host blocks with different indices. A memory block can be mapped to one subset from the exclusive type or one of multiple subsets from the shared type. Since the proposed technique is based on combining multiple sets of the shared part to form a larger set, that is shared between memory blocks with different indices, we have chosen the name “set folding.” The decision as to where to map a memory block depends on the number of misses encountered at each of the potential target sets. To evaluate the proposed design based on the overall hit rate, twenty-three benchmarks from SPEC CPU 2006 were simulated using the SuperESCalar simulator. The proposed designs require a few extra storage bits which adds a small overhead on the hardware complexity in comparison with the conventional cache. However, the proposed designs achieve lower miss rates for most of the benchmarks. [ABSTRACT FROM AUTHOR]