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In this paper, based on reversibility and approximation concepts, full adder (FA) circuits are designed for fault-tolerant applications. Area saving along with power reduction is the main objectives in the design and implementation of the proposed FAs. So, the basic reversible gates including Toffoli, Fredkin, Feynman, and Thapliyal Ranganathan (TR) are realized based on the gate diffusion input (GDI) technique. Subsequently, three approximate reversible FAs are designed with 3, 2, and 1 gates, respectively, which have special features such as 0 constant input (CI) and minimum garbage output and transistor counts. The circuitry performance and the quality of output images are extracted, when the FAs are placed in the approximate ripple carry adder (RCA) for image addition. The results show the superiority of the proposed FAs. Comprehensive results are extracted from the defined figure of merits (FoMs), which consists of area, power-delay product (PDP), peak signal-to-noise ratio (PSNR), and normalized mean error distance (NMED). The Pro-2 FA is selected as the best option due to its significant superiority compared to other circuits. The Pro-2 has 61.47% and 73.51% savings of PDP and PDP-area product (PDAP), respectively, compared to the exact circuit. [ABSTRACT FROM AUTHOR]

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A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

Copyright of Frontiers of Information Technology & Electronic Engineering is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Size reduction in complementary metal–oxide–semiconductor integrated circuits (ICs) is a challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages such as low power, high mobility, and ballistic transmissions is an alternative. Based on the standard 32 nm CNTFET technology, a new 23-transistor full adder cell is proposed with combining advantages of gate diffusion input and transmission gate techniques, which are low power and full swing. Owing to small number of transistors and internal nodes, the delay time and activity factor decreased to 13.5τ. Simulations of critical parameters variations like VDD, temperature, and fan-out expose better performance of the proposed cell. Investigating the process voltage temperature with Monte Carlo simulation verified better stability, immunity, and tolerability of the cell in comparison with well-known full adder cells. Suggested full adder cell was implemented in 4:2 compressor with 9.0298 fJ of power delay product and minimum area occupation among the references. Based on real chip measurements, total die area occupation for proposed full adder and compressor is 0.505 µm2 and 1.092 µm2, respectively. Proposed circuits were applied to an 8-bit subtractor for orthopantomogram image processing to detect tooth core build up and restored with dental filling in order to maintain a crown restoration. Merits of proposed circuits both in IC design and image processing make these circuits suitable choice for bioelectronics chips. [ABSTRACT FROM AUTHOR]