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This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU and PU, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm. From the experimental results, the presented work achieves satisfactory performance for each function. [ABSTRACT FROM AUTHOR]

Having local data communication (without global broadcast of signals) among the elements is important in very large scale integration (VLSI) designs. Recently, 2-D systolic digital filter architectures were presented which eliminated the global broadcast of the input and output signals. In this paper a generalized formulation is presented that allows the derivation of various new 2-D VLSI filter structures, without global broadcast, using different 1-D filter sub-blocks and different interconnecting frameworks. The 1-D sub-blocks in z-domain are represented by general digital two-pair networks which consist of direct-form or lattice-type FIR filters in one of the frequency variables. Then, by applying the sub-blocks in various frameworks, 2-D structures realizing different transfer functions are easily obtained. As delta discrete-time operator based 1-D and 2-D digital filters (in $$\gamma $$-domain) were shown to offer better numerical accuracy and lower coefficient sensitivity in narrow-band filter designs when compared to the traditional shift-operator formulation we have covered both the conventional z-domain filters as well as delta discrete-time operator based filters. Structures realizing general 2-D IIR (both z- and $$\gamma $$-domains) and FIR transfer functions (z-domain only) are presented. As symmetry in the frequency response reduces the complexity of the design, IIR transfer functions with separable denominators, and transfer functions with quadrantal magnitude symmetry are also presented. The separable denominator frameworks are needed for quadrantal symmetry structures to guarantee BIBO stability and thus presented for both the operators. Some limitations of having exact symmetry with separable 1-D denominator factors are also discussed. [ABSTRACT FROM AUTHOR]