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Data-centric applications are pushing the limits of energy-efficiency in today’s computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.Data-centric applications benefit from dense, low-power memory. Here the authors use a combination of chalcogenide superlattices and nanocomposites to achieve low switching voltage (0.7 V) and fast speed (40 ns) in 40-nm-scale phase-change memory. [ABSTRACT FROM AUTHOR]

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2–5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6–17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.A compute-in-memory neural-network inference accelerator based on resistive random-access memory simultaneously improves energy efficiency, flexibility and accuracy compared with existing hardware by co-optimizing across all hierarchies of the design. [ABSTRACT FROM AUTHOR]

The rapid growth and development of technology has had significant implications for healthcare, personalized medicine, and our understanding of biology. In this work, we leverage the miniaturization of electronics to realize the first demonstration of wireless detection and communication of an electronic device inside a cell. This is a significant forward step towards a vision of non-invasive, intracellular wireless platforms for single-cell analyses. We demonstrate that a 25 μ m wireless radio frequency identification (RFID) device can not only be taken up by a mammalian cell but can also be detected and specifically identified externally while located intracellularly. The S-parameters and power delivery efficiency of the electronic communication system is quantified before and after immersion in a biological environment; the results show distinct electrical responses for different RFID tags, allowing for classification of cells by examining the electrical output noninvasively. This versatile platform can be adapted for realization of a broad modality of sensors and actuators. This work precedes and facilitates the development of long-term intracellular real-time measurement systems for personalized medicine and furthering our understanding of intrinsic biological behaviors. It helps provide an advanced technique to better assess the long-term evolution of cellular physiology as a result of drug and disease stimuli in a way that is not feasible using current methods. [ABSTRACT FROM AUTHOR]

Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics. The epitaxial growth of single-crystal hexagonal boron nitride monolayers on a copper (111) thin film across a sapphire wafer suggests a route to the broad adoption of two-dimensional layered semiconductor materials in industry. [ABSTRACT FROM AUTHOR]

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented. [ABSTRACT FROM AUTHOR]

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced. [ABSTRACT FROM AUTHOR]

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems. [ABSTRACT FROM AUTHOR]

The article discusses the potential of the spin-transfertorque magnetic random access memory (STT-MRAM) devices using different physical mechanisms. Details about the STT-MRAM are provided which store information in the magnetization of a nanoscale magnet. Also tackled are the difference in which the design specifications for memory.

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. [ABSTRACT FROM AUTHOR]

A novel contact technique to reduce the effective Schottky barrier height on Ge and III–V high mobility semiconductors is described. Single metals are used in combination with an ultrathin dielectric to tune the metal/semiconductor barrier height toward zero by shifting or suppressing the strong Fermi-level pinning. Barrier height reduction in the metal-insulator-semiconductor (MIS) contact structure is verified through direct measurements and deduced from increased diode current and reduced contact resistance. Current demonstrations of the MIS contact have barriers as low as 0.05 eV for Er/SiN/n-Ge and 0.18 eV for Al/Al2O3/n-GaAs. The underlying physics is discussed along with the dependence of the minimum achievable contact resistance and barrier height on the metal, dielectric material, dielectric thickness, and substrate doping. For Ge, the MIS contact provides a possible solution to the low n-type Ge dopant solubility problem and allows for the fabrication of Schottky barrier field-effect transistors. For III–V semiconductors, the MIS contact allows for the use of a non-alloyed contact that is crucial for the scalability of III–V metal oxide semiconductor field-effect transistors. [ABSTRACT FROM AUTHOR]

An amendment to this paper has been published and can be accessed via a link at the top of the paper. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics. Carbon nanotube thin-film transistor is promising for solution-processed, large-scale flexible electronics, but the device yields remain poor to date. Lei et al. show low-voltage flexible digital and analog circuits based on high-purity and high-yield separation of semiconducting carbon nanotubes. [ABSTRACT FROM AUTHOR]

The priority of synaptic device researches has been given to prove the device potential for the emulation of synaptic dynamics and not to functionalize further synaptic devices for more complex learning. Here, we demonstrate an optic-neural synaptic device by implementing synaptic and optical-sensing functions together on h-BN/WSe2 heterostructure. This device mimics the colored and color-mixed pattern recognition capabilities of the human vision system when arranged in an optic-neural network. Our synaptic device demonstrates a close to linear weight update trajectory while providing a large number of stable conduction states with less than 1% variation per state. The device operates with low voltage spikes of 0.3 V and consumes only 66 fJ per spike. This consequently facilitates the demonstration of accurate and energy efficient colored and color-mixed pattern recognition. The work will be an important step toward neural networks that comprise neural sensing and training functions for more complex pattern recognition. Artificial neural networks can emulate the human vision because of their spike-based operation by employing memristors as synapses. Here, Seo et al. integrate synaptic and optical sensing functions in a single heterostructure, which enables accurate and energy-efficient recognition of colored patterns. [ABSTRACT FROM AUTHOR]

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system. [ABSTRACT FROM AUTHOR]

The Field Effect sensors are broadly used for detecting various target analytes in chemical and biological solutions. We report the conditions under which the pH sensitivity of an Ion Sensitive Field Effect transistor (ISFET) sensor can be significantly enhanced. Our theory and simulations show that by using pH buffer solutions containing counter-ions that are beyond a specific size, the sensor shows significantly higher sensitivity which can exceed the Nernst limit. We validate the theory by measuring the pH response of an extended gate ISFET pH sensor. The consistency and reproducibility of the measurement results have been recorded in hysteresis free and stable operations. Different conditions have been tested to confirm the accuracy and validity of our experiment results such as using different solutions, various oxide dielectrics as the sensing layer and off-the-shelf versus IC fabricated transistors as the basis of the ISFET sensor. [ABSTRACT FROM AUTHOR]