Search

A novel device structure with gate engineered recessed double gate junctionless field-effect-transistor (R_DGJLFET) has been investigated for variations in effective oxide thickness (EOT) and the optimum structure is utilized for the low power biosensing application. The device with 20 nm gate length has been designed and analyzed using ATLAS tool of SILVACO TCAD. With extensive simulation several physical parameters such as field and potential distribution, carrier concentration and conduction band energy have been analyzed along with drain current and gate-to-source capacitance. Several FOM of R_DGJLFET and conventional junctionless FET (C_DGJLFET) have been compared. It has been found that for EOT of 0.8 nm the R_DGJLFET reduces IOFF by ~ 10− 4 and the subthreshold slope is also improved. Moreover, for EOT ≤ 1 nm, the R_DGJLFET outperforms the C_DGJLFET with improved analog parameters. Furthermore, a low power biosensing application has been implemented with the proposed device. Dielectric modulation is utilized to realize the different type of biomolecules inside the cavity region of the structure. Biosensor is tuned at low voltage for better performance, which presents it as a promising contender for the future CMOS based low power sensor applications. [ABSTRACT FROM AUTHOR]

For the first time, a new configuration of label-free junctionless semiconductor device is proposed to boost sensitivity in the identification of biomolecule specifies. Instead of creating the nanocavity inside the gate oxide, the nanocavity is created in the channel region which is very useful for the SOI junctionless technology based biodevice having a high current in all operating modes. For better control of the conduction mechanism, a hole trench is created under the channel region just inside the buried oxide. This will help to modulate the energy bands terminating in enhancing the sensing performance. Unlike the conventional biosensors needing a large-scale gate oxide thickness for trapping the biomolecules, the proposed biosensor can work for very low gate oxide thickness. The different biomolecules such as Biotin, Protein A, Bacteriophage T7, and Apomyoglobin have been utilized as targeted biomolecules for evaluating the sensitivity. Comparing the proposed biosensor with the conventional and other biosensors showed an enhanced sensing performance. Practical related issues during the process of sensing in terms of fill factor percentage, steric hindrance of biomolecules, and the charges of biomolecules have been focused in the recommended biodevice. All the results exhibited high superiority of performance of the suggested biodevice as compared to the conventional biosensor. [ABSTRACT FROM AUTHOR]

The design and analysis of a gate stack gate-all-around junctionless nanowire field-effect transistor (GAA-JL-NWFET) with a catalytic metal as gate contact for oxygen gas sensing is presented in this study. An n-channel GAA-JL-NWFET design using gold (Au) as the gate metal electrode is employed for oxygen sensing by utilizing appropriate work function values, which interact with oxygen gas and change the device's electrical properties. This work focuses on changes in temperature (300–500 K) and Au metal gate work function (5.05–5.20 eV) to investigate the presence of oxygen molecules and their impact on the GAA-JL-NWFET gas sensor performance. Changes in the surface potential, threshold voltage, hole concentration, electron concentration, subthreshold voltage, electric field, and drain current using the ATLAS TCAD simulator are investigated for the adsorption of gas molecules to determine the electrical characteristics of the proposed device. Changes in threshold voltage (Vth), switching ratio, and subthreshold current sensitivity ( S I OFF ) can be considered as sensitivity parameters for sensing oxygen gas molecules. The results reveal that as the Au work function shifts at the gate by 100 mV, the sensitivity ( S I OFF ) enhancement using gate stack GAA-JL-NWFET-based oxygen gas sensors compared to GAA-MOSFET and conventional MOSFET are 15.13% and 88.31%, respectively. Based on our simulation results, the proposed device offers excellent sensitivity, low power consumption, and a fast response time, making it an appropriate candidate for oxygen gas sensing, including environmental monitoring, medical diagnosis, and industrial safety. [ABSTRACT FROM AUTHOR]

A gate engineered ferroelectric junctionless field-effect transistor biosensor (BioFET) is proposed and investigated for label-free detection of various biomolecules. A nanocavity is created by etching a part of the gate oxide material on the top and bottom of the device, which allows biomolecules to get immobilized. The immobilization of biomolecules in the cavity causes changes in electrostatic characteristics such as surface potential, input and output characteristics, transconductance, output conductance, gate capacitance, and cutoff frequency used as sensing metrics. The biosensor is also examined at different biomolecule concentrations (−1 × 1012 cm−2, 0 cm−2, and 1 × 1012 cm−2). The transistor's sensitivity is then understood by looking at the fluctuation in threshold voltage, subthreshold swing, and switching ratio. The performance is compared between the ferroelectric junctionless BioFET and the gate engineered ferroelectric junctionless BioFET. The results indicate that the gate engineered ferroelectric junctionless BioFET shows the maximum improvement for protein (1202.4%, 111%, and 565%) and DNA (787.5%, 117.3%, and 600%). The gate engineered ferroelectric junctionless BioFET is shown to be suitable for ultrasensitive bio-sensing applications. [ABSTRACT FROM AUTHOR]

This research presents a biosensor based on a dielectrically modulated (DM) silicon on insulator (SOI) junctionless fin-shaped field-effect transistor (FinFET) (DM-SOI-JL-FinFET) for the detection of biomolecules. This biosensor is integrated with a label free detection of neutral biomolecules such as biotin (k = 2.53), APTES (k = 3.57), ferro-cyt C (k = 4.7), bacteriophages (k = 6.3), and keratin (k = 8). By etching the gate oxide, a nanocavity with a thickness of 5 nm and a height of 35 nm is created for immobilized biomolecules. The presence of biomolecules is determined by observing variations in the dielectric constant. Various important parameters including threshold voltage, the ratio of on-state and off-state current (ION/IOFF) sensitivity, drain current, transconductance, and surface potential are thoroughly investigated for different biomolecules with a function of dielectric constant, fin height, and fin width. The study demonstrates a threshold voltage sensitivity (Sv) of 0.1552 (biotin, k = 2.53) and 0.5628 (keratin, k = 8), as well as an ION/IOFF current sensitivity (SI) of 1.1609 (biotin, k = 2.53) and 3.9774 (keratin, k = 8) for the simulated structure. [ABSTRACT FROM AUTHOR]

This research investigates the virtually doped dual gate junctionless impact ionization MOS (DG-JL-IMOS). Virtually doped source and drain regions are realized through the genesis of charge plasma using different work-functions for their electrodes, easing the process complexity with simultaneous reduction of process-induced variations to implant uniform doping. The proposed DG-JL-IMOS device exhibits two order increase in I ON / I OFF ratio at a lower source bias of - 4.5 V with respect to - 5 V required for a single gate JIMOS device. This work further examines the breakdown behavior of the proposed DG-JL-IMOS by analyzing carrier density distribution, impact ionization, and electric field profile through extensive TCAD simulations. The proposed device exhibits a super steep sub-threshold swing (SS) of 0.6 mV/dec over several orders of drain current, which is not achieved by any other counterpart steep-slope technologies. The effect of interface traps on the proposed DG-JL-IMOS is studied and investigated for hysteresis in the transfer characteristics. Furthermore, analog parameters such as transconductance ( g m ), unity gain cutoff-frequency ( f T ), and current gain of the proposed device are evaluated and compared with conventional DG-IMOS. It is observed that the proposed device shows a 2.6 × increase in I ON , 1.7 × higher g m , 1.6 × higher f T , and a 5 dB improvement in current gain compared to conventional DG-IMOS. The proposed DG-JL-IMOS device breakdowns at a voltage, ( V BD ) of - 4.21 V, whereas DG-IMOS breakdowns at - 4.75 V. The enhanced performance metrics of DG-JL-IMOS elucidate its suitability for high-speed and high-performance analog applications. [ABSTRACT FROM AUTHOR]

Vertically stacked Nanosheet Field Effect Transistor (NSFET) is considered the most promising substitution for FinFET. In order to prevent making metallurgical junctions, based on the nanosheet, junctionless(JL) NSFET has been proposed. However, since the channels of JL-NSFET are stacked and highly doped, JL-NSFET is more vulnerable to random variability. In this article, to optimize the structure of JL-NSFET and reduce the impact of random variability on JL-NSFET, some process variability in JL-NSFET is investigated simultaneously. The process variability discussed in this paper includes Oxide Thickness Variation (OTV), Random Doping Fluctuation (RDF), and Work Function Variation (WFV). Using the statistical impedance field method (sIFM), the impacts of the random variability on device characteristics, such as threshold voltage and subthreshold slope, are analyzed. Simulations of JL-NSFET indicate that lower doping concentration, more stacks, smaller average grain size, bigger sheet spacing, and choosing a suitable value of sheet width can help produce JL-NSFET with less influence from WFV, RDF, and OTV. [ABSTRACT FROM AUTHOR]

In this paper, the performance of a junctionless carbon nanotube field-effect diode in the presence of electron–phonon scattering is examined. A self-consistent mode-space simulation approach based on non-equilibrium Green's function is used. We have studied the influence of incoherent transport on electrical characteristics such as on-current ( I ON ), off-current ( I OFF ), on/off current ratio (ION/IOFF), intrinsic delay (τ), energy-delay product, and sub-threshold power dissipation (SPD ) at various gate lengths. We have shown that phonon-assisted tunneling dominates the band-to-band tunneling regime under off-state conditions. Therefore, this phenomenon deteriorates I OFF and, as a result, SPD . Furthermore, the scattering results in an increase in the intrinsic delay and energy consumed per switching event. Finally, in the on-state, acoustic phonons interaction is the overriding scattering mechanism and causes about a 35% reduction in I ON . [ABSTRACT FROM AUTHOR]

This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO2 which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10−16) and high ION/IOFF ratio (~1011) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as ION/IOFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications. [ABSTRACT FROM AUTHOR]

This work presents a new junctionless device called Workfunction Modulated Dual Metal Gate Junctionless FinFET (WFMDMG-Junctionless FinFET) to minimize the short channel effects, and to achieve improved dc performance. The result is analyzed by dividing the workfunction of the gate metal electrode in two equal halves and further dividing the source end of the electrode in five equal parts with linear variation in workfunction, keeping the drain end at constant workfunction. The 3-D TCAD simulations are carried out by SILVACO TCAD tool. And the results are compared with the Single Metal Gate (SMG)-junctionless FinFET, and Dual Metal Gate (DMG)-junctionless FinFET. The new proposed junctionless device shows improved subthreshold characteristics, i.e., minimum subthreshold swing (SS) of 60.1 mV/decade, and high ION/IOFF current ratio of 1.48e13. [ABSTRACT FROM AUTHOR]

The recently proposed recessed double gate junctionless field-effect-transistor (R_DGJLFET) based circuit performance has been investigated with emphasis on designing various digital logic standard cells. Symmetric inverter circuit (NOT gate) has been designed and analyzed extensively using mixed-mode simulator in Silvaco TCAD. The proposed device-based inverter reflects lesser overall power consumption with static leakage component (~0.104 nW), switching power dissipation (~11.613 μW), and short-circuit power dissipation (~0.472 nW). The static analysis of the proposed device-based symmetric inverter features steeper voltage transfer characteristics, better noise margins and smaller short-circuit current relatively while the excellent transient delay response with rise time (~9.3 ps), fall time (~9.0 ps), and propagation delay of (~6.5 ps) for load capacitance of 10 fF. Moreover, the proposed device based 2-input logic cells namely NAND, NOR, and XOR gate has also been implemented and their transient response with a different load capacitance of 10 fF and 0.1 pF has been presented. The simulation results show that increasing the load capacitance results in a longer propagation delay of the circuits. Furthermore, the transient performance of all R_DGJLFET based digital logic gates has also been investigated with equal gate width for PMOS and NMOS devices. It has been found that designing the asymmetric logic gates weakens the pull-up characteristics which eventually elongates the delay values. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

This paper investigates the various device dimensions such as gate length (Lg), nanosheet thickness (TNS), and nanosheet width to optimize the design space for vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The optimization has been carried out by considering several analog/RF parameters that include On-current (ION), Off-current (IOFF), Transconductance Efficiency (gm/Id), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), ION/IOFF ratio, Transconductance (gm), gate capacitance (Cgg), Output conductance (gds), and Cutoff-frequency (fT), Intrinsic gain (Av) are explored here. It is found that the downscaling of Lg from 16 nm to 8 nm resulted in an increase in SS and DIBL. However, scaling down of TNS (WNS) from 10 nm to 5 nm (from 18 nm to 10 nm) resulted in a decrease in SS by ~30.5% (~16.39%) and in DIBL by ~44.23% (~78.59%) respectively. The short channel effects (SCE) are greatly suppressed by upscaling of Lg and downscaling of TNS and WNS. The transconductance (gm) is improved by decreasing the Lg and TNS but a significant degradation is found for WNS. Further, the gain (Av) is improved by an amount of ~22.86% by upscaling the Lg and ~ 7.07%, ~31.75% with the downscaling of TNS and WNS respectively. The gate capacitances (Cgg) are reduced with the downscaling of Lg and WNS, however the same is increased for TNS. Moreover, the cutoff frequency (fT) is improved with scaling down of Lg and TNS in comparison with the WNS. [ABSTRACT FROM AUTHOR]

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give the highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths. [ABSTRACT FROM AUTHOR]

In this work, a Core–Shell Junctionless MOSFET is proposed as a RADFET dosimeter for possible radiation-sensitive applications. The analytical models of the surface potential, drain current, and the threshold voltage is developed to investigate the electrostatic behaviors of the proposed device under post-irradiation condition. The sensitivity is measured through the threshold voltage shift for a long-range of applied doses. The results compared with contemporary literature reveal a superior sensitivity performance of our proposed device. It exhibits a linear sensitivity profile with a sensitivity of 2.03 mV/Gy over a wide radiation dose range, from 300 Gy to 30,000 Gy. Furthermore, the analytical model accurately captures the device's characteristics compared to the simulation results, carried out SILVACO TCAD 3D device simulator. Therefore, we propose the Core–Shell Junctionless RADFET dosimeter as a promising candidate for future VLSI CMOS technology. [ABSTRACT FROM AUTHOR]

Advances in microelectronics have enabled smaller technical nodes, lower threshold voltages, and greater working frequencies. Even though VLSI circuit performance and power consumption have improved as a result, the reliability of the designs has suffered. A fall in noise resistance and an increase in uncertainty from multiple sources of variability make circuits more vulnerable as technology scales down. Fault tolerant techniques are commonly used in safety-critical applications. Three-dimensional electrical devices like double gate, tri-gate, and nanowire field-effect transistors (FETs) give an alternative approach since they regulate the device channel better electrostatically. In this paper, a new form of FinFET with asymmetric gate and source/drain connections is developed, and its simulation results are shown. Asymmetric FinFETs exhibit better short-channel behavior when the current density is increased, according to the results of the benchmarking. High aspect ratio FinFETs give greater current per area while demanding significantly fewer horizontal geometry constraints, making them ideal for situations where conventional scaling has hit its physical limits. The suggested multigate FinFET provides improved performance in low-power and high-frequency applications, according to the experimental results. The work report also includes an evaluation of the proposed multigate FinFET's dependability. [ABSTRACT FROM AUTHOR]

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (ION/IOFF) = ~106 shows a higher level of electrostatic integrity. At 5 nm LG with optimized spacer dielectric the device exhibits ~5 orders of improvement in IOFF and the improvement is less than ~2 orders at 20 nm LG. Thus, from the result analysis, the spacer dielectrics are essential at lower LG for better performance. For continued scaling, the HfO2 spacer dielectric ensures high performance with the lowest downfall in ION with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si3N4 respectively. With SiO2, Si3N4, and HfO2 spacers the asymmetric spacer ensures an ION/IOFF of ~106 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes. [ABSTRACT FROM AUTHOR]

A comprehensive study of the drain current drift mechanism and hysteresis phenomena in fabricated p-channel junctionless ion-sensitive field-effect transistor (JL-ISFET) has been investigated for the first time. The current drift measurements have been performed through transient analysis of drain current, under different pH and liquid-gate bias (Vlg). Further, time-dependent gate-capacitance (CG) has also been analyzed to see the effect of hydroxyl ions (OH−) in the sensing film (Al2O3). The hysteresis has also been investigated for different pH loop (7 → 3 → 7 → 11 → 7 and 7 → 11 → 7 → 3 → 7) and times (960s, 1500s, and 1920s). It has been observed that the drift of JL-ISFET occurs because of chemical modification of the sensing film, due to OH−. The proposed device exhibits a threshold voltage sensitivity of 58.2 mV/pH that is near the Nernstian limit. Further, the hysteresis width and maximum drain current drift are measured as ∼ 1.3 mV and 2.4 μ A (∼ 75%), respectively. [ABSTRACT FROM AUTHOR]

Recently, increasing power leakage has become a major concern especially in MOSFET based nanoscale devices due to poor gate control. To mitigate these problems, the devices with steep slope, low leakage and power consumption are required. In this context, this work introduced a novel concept of Negative Capacitance (NC) effect with Junctionless Multi Gate FET to investigate various device performance parameters for nanoscale dimensions. The baseline approach of combining LK-equation with Sentaurus TCAD tool, was used to design and optimize a 14nm n-type Negative Capacitance Junctionless FinFET (NC-JL FinFET) with doped HfO2 as gate ferroelectric material for low power applications. The impact of ferroelectric thickness, spacer and gate dielectric was analyzed using extensive device simulations. The results showed that the designed NC-JL FinFET exhibits enhanced performance with steep SS, Negative DIBL, lower leakage current and also higher drive current performance than JL FinFET. Further, the application of strain-engineering in NC-JL FinFET shows 12 % improvement in ION/IOFF as compared to unstrained NC-JL FinFET. [ABSTRACT FROM AUTHOR]

This work investigates the non-uniform doping effect on a junctionless (JL) FinFET 6T SRAM cell. Employing a Gaussian doping distribution across the fin region of JL FinFET structure improves the OFF-current and ON-current performance. This opens up an opportunity for better device/circuit co-design. The implementation of 6T SRAM cell with Gaussian doped JL FinFET (GD-JL FinFET) has been demonstrated in the present work. It shows 12.23 %, 4.62 %, and 4.4 % improvements in noise immunity during read, write and hold mode, respectively than uniformly doped JL SRAM cell. Additionally, the improvement in write/read access time has been observed. The impact of supply voltage reduction on SRAM performance metrics has also been investigated. Furthermore, the statistical variability analysis of GD-JL FinFET based SRAM cell has been demonstrated in this work. [ABSTRACT FROM AUTHOR]

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x 10 − 6 A/µm with reduced OFF-state leakage current up to1.37 x 10 − 17 A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator. [ABSTRACT FROM AUTHOR]

An integrated design based on Gate-All-Around (GAA) silicon Junctionless (JL) vertical profile Nanowire (NW) structure has been proposed for JL-NW-Tunnel-Field Effect Transistor (JL-NW-TFET). A uniform high doping concentration (10−19) has been used to make the device a Junctionless structure. The parametric variations of the JL-NW-TFET have been analyzed such as ON-current (ION), OFF-current (IOFF), ON-OFF ratio of current (ION/OFF) and Subthreshold-Slope (SS). Therefore, work function of gate metal (4.4 eV to 4.8 eV), thickness of oxide (1.0 nm to 2.0 nm), diameter of Nanowire (10 nm to 30 nm) and channel length (22 nm to 65 nm) has been varied by implementing device structure in SILVACO Atlas Tools. The optimum parameters of the device have been observed as: maximum ION (3.73 × 10−6 A/μm), minimum IOFF (2.97 × 10−20 A/μm), Low SS (19.40 mV/dec) and high ION/OFF (3.35 × 1013). It has been proposed that these optimum parameter characteristics are immune to short channel effects and preferred for low power applications in nano regime. [ABSTRACT FROM AUTHOR]

This manuscript investigates the effect of inner gate engineering (IGE) on the linearity and harmonic distortion performance of junctionless (JL) silicon-nanotube (Si-NT) FETs for wireless applications. The three configurations of JL-Si-NT-FET namely DS-JL-Si-NT-FET (inner gate covers drain & source regions both in addition to channel region), D--JL-Si-NT-FET (inner gate covers only drain region and channel region), and S--JL-Si-NT-FET (inner gate covers only source region and channel region) are compared to find the best configuration for wireless applications. The simulation results divulge that S--JL-Si-NT-FET configurations shows the improved linearity and harmonic distortion performance in terms of the performance metrics HD2, HD3, VIP3, IIP3, 1-db compression point, and higher order coefficients of transconductance (gm2 & gm3). Consequently, the S-JL-Si-NT-FET is the best configuration to be used for RFIC design and wireless applications. [ABSTRACT FROM AUTHOR]

This paper focuses on the impact of gate stacking (SiO2+HfO2) on dopingless vertical nanowire TFET (designed with gate-on-source technique) with an equivalent oxide thickness (EOT) of 0.8 nm and SiO2 thickness of 0.5 nm. Here, the charge plasma technique is used for doping on an intrinsic silicon substrate by using platinum (with work function of 5.93 eV) on the source side metal and hafnium (with work function of 3.9 eV) as the gate 1 metal. The proposed gate-stacked charge plasma vertical nanowire tunnel FET (GS-CPVNWTFET) device is simulated in ATLAS-2D, and the performance metrics are investigated. The paper compares three different combinations of SiO2 and HfO2 (with SiO2 thicknesses of 0.3 nm, 0.4 nm and 0.5 nm) and then the analog and RF parameters, such as ID-VGS and ID-VDS characteristics, input transconductance (gm), transconductance to drive current ratio (gm/ID), gate to source capacitance (CGS), gate to drain capacitance (CGD), total gate capacitance (CGG), unity gain cut-off frequency (fT), output transconductance (gd), output resistance (rO), early voltage (VEA), intrinsic gain (AV) and gain bandwidth product (GBP), and the structural performance for all three combinations are obtained. The proposed GS-CPVNWTFET device exhibits ION of 19.182 µA/µm, IOFF of 7.05 × 10−17 A/µm, ratio of ON current to OFF current (ION/IOFF) ~ 2.72 × 1011, subthreshold slope (SS) of 10.80 mV/decade and DIBL of 3.17 mV/V. Later, a comparison is carried out between conventional CPVNWTFET and gate-stacked CPVNWTFET, and it is observed that the proposed GS-CPVNWTFET device with gate-on-source technique shows better analog and structural performance. [ABSTRACT FROM AUTHOR]

With the scaling of MOSFET devices, study of process variations on the electrical performance of the device has become more important. Also, there is a need to reduce this process induced variability as this can further lead to instability in circuit performance of the device. This paper presents assessment and optimization of process induced variability in Inversion mode and Junctionless Nanowire MOSFET. Process parameters such as channel length, nanowire radius, oxide thickness, and channel doping are considered to estimate the performance degradation. Among all process parameters, nanowire radius results in maximum variability and oxide thickness results in minimum variability for both the devices. Junctionless Nanowire MOSFET has shown more sensitivity to threshold voltage variability as compared to conventional type. Also, using high-k dielectric, device can be optimized to have better sensitivity against process variations. [ABSTRACT FROM AUTHOR]

This work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical characteristics. By adopting multiple combinations between the fin height (HFIN) and the fin width (WFIN), chosen from the range of published data in the literature, the devices will operate from double-gate (FinFET like) mode towards to nanowire mode. Additionally, junctionless transistors with and without additional doping at the drain and source extensions were studied. Experimentally calibrated 3D TCAD simulations are used to allow for the study of these several combinations. Results show that for long-channel devices the best performance is obtained for tall and narrow fins, leading to the highest on-to-off current ratio (ION/IOFF) and the smallest values of subthreshold swing and DIBL. On the other hand, for short channel devices, independently of the doping level of the extensions, the best results are found for short HFIN and narrow WFIN, leading to the smaller values of subthreshold swing and DIBL, with a high ION/IOFF ratio. However, the use of doped extensions degrades the overall device performance of short-channel junctionless devices as will be demonstrated. [ABSTRACT FROM AUTHOR]

The amalgamation of high dielectric permittivity material along with vaccum based dual material junctionless transistor with surrounding gate (DUM-HIK-VAC-JLSG-MOSFET) was investigated in this paper. The diverse oxide gate stack architecture of DUM-HIK-VAC-JLSG-MOSFET abate various effects arise due to channel shrinking. The evaluation of various parameters such as potential distribution in the channel region, electric field (transverse, lateral), transconductance, electron current density and drain current has been analyzed and a comparative statement between DUM-HIK-VAC-JLSG-MOSFET and the single material gate junctionless high k and vaccum double gate MOSFET(SIM-HIK-VAC-JLSG-MOSFET). The commingle of high dielectric permittivity material with vaccum as gate oxide stack and junctionless transistor with surrounding gate structure Dual material achieve a foremost responsibility to mitigate the device shrinking effects, impel to raise the ION current (10−3A/μm) and diminish the leakage current IOFF of 10−18A/μm to boost the ION/IOFF ratio as 1015. To guarantee the scalability and responsiveness of the device simulations has been done with Synopsys TCAD simulator tool. [ABSTRACT FROM AUTHOR]

In this study, we analyze a β-Ga2O3 gate-all-around nanowire junctionless transistor (β-GAA-JLT) in accumulation mode. The performances are investigated by considering quantum effects, and the results are compared with those of a silicon gate-all-around nanowire junctionless transistor (Si-GAA-JLT) device. We illustrate that the ultra-scaled β-Ga2O3 field effect transistors (FETs) perform better in terms of short-channel effects (SCEs) and temperature dependence than the silicon material in accumulation mode. Because of the lower natural length of Ga2O3 versus silicon and higher electrostatic integrity, SCEs are improved versus conventional junctionless silicon devices. We also present that the proposed structure has superior results including a higher depletion region, lower self-heating effect (SHE), and greater immunity against SCEs versus Si-GAA-JLT. The fabrication flow process of the β-GAA-JLT is investigated. [ABSTRACT FROM AUTHOR]

As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction's related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications. [ABSTRACT FROM AUTHOR]

In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrödinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO2) thickness on ID has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same IOn current as IM device and (ii) to get the same threshold voltage VTh as IM. This has resulted in 102 and 103 times smaller IOff in matching IOn and VTh optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL ~15 mV/V, almost an ideal SS ~60 mV/dec, and higher IOn/IOff ratio ~2.18 × 108 as compared to available CGAA literature results. [ABSTRACT FROM AUTHOR]

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20 × 10–14 A/µm, ON-to-OFF current ratio of the order of 6.01 × 1010, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V−1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool. [ABSTRACT FROM AUTHOR]

CMOS scaling is the approach to accomplish the VLSI goals in the past decades. The existing CMOS technology is facing challenges related to short channel effects and reached to its performance limits at sub-10 nm technology nodes. The negative capacitance field-effect transistor is a potential device for near future technology to overcome these challenges. In the present work, negative capacitance Junctionless (NC-JL) FinFET with Metal-Ferroelectric–Insulator-Semiconductor (MFIS) structure is proposed and analysed comprehensively using TCAD simulation for its scaling capability over the various technology nodes starting from 24 nm to 5 nm. It is revealed that the integration of negative capacitance (NC) with JL FinFET helps to reduce the leakage current, short channel effects such as subthreshold slope, DIBL and provide high drive current as well as fast switching by reducing intrinsic delay for extremely short channel length as compared to standard-JL FinFET. Furthermore, the different performance parameters including Gate Induced Drain Leakage Current (GIDL) of proposed NC-JL FinFET are comprehensively studied. [ABSTRACT FROM AUTHOR]

In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this small scale of gate length. Both oxide widths of high K-material HfO2 have their own individual benefits, due to high gate controllability as compared to conventional FinFETs having SiO2 as a gate oxide. The device works best with Tox = 1 nm in terms of power amplification. When tested with this width of gate oxide, we end up with increase of 59.18%, 7.22% and 12.11 times at corresponding peak values of Unilateral power gain (Gu), IP3 and fmax. This actually evident the enhanced performance of TF-FinFET for A.C applications at this high range of frequency of the input signal. When device tested at Tox = 1 nm, we end up with the increase of 45%, 21.45%, 16% and decrease of 65% at the corresponding peak values of Intrinsic delay (ti), Transconductance (gm), Drain current (ID) and OFF-state current (IOFF). These results of simulation also showed the compatibility of TF-FinFET in terms of high-performance analog application. After these analyses, we can expect a strong potential for wide variety of applications to high-speed System on chip from this device. [ABSTRACT FROM AUTHOR]

This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1-xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications. [ABSTRACT FROM AUTHOR]

A new heterodielectric shifted-core-gate nanotube tunneling field-effect transistor (HD-SCG-NT-TFET) is proposed with a higher ON-state current and a better subthreshold swing (SS) compared with the conventional core-gate NT-TFET structure. The charge plasma phenomenon is employed to induce charge carriers inside the channel and source region by applying an appropriate metal workfunction. A brief comparative analysis of the influence of the high-K gate dielectric on the interface trap charges (ITCs) and the resulting effect on the performance of the nanotube structures is also presented for different direct-current (DC) parameters. A reliability analysis for the nanotube TFET is presented for the first time to test how efficiently the proposed device follows the original characteristics. To address reliability concerns for low-power applications, the nanotube TFET structures are investigated in terms of their ION, IOFF, subthreshold swing (SS), and ION/IOFF ratio. All of the analyses are performed in the presence of negative, neutral, and positive ITCs. [ABSTRACT FROM AUTHOR]

In this paper, a novel sturcture of planar Silicon on Insulator Junctionless transistor is proposed with improved ION/IOFF ratio, Short Channel effects (SCEs) and most importantly, it is scaleable. A highly doped pocket (p-type) will form PN junction at its interface with n-type channel and hence referred to as pocket doped Silicon on Insulator Junctionless transistor (PD-SOI-JLT). A highly doped region in the channel helps to produce full depletion in the OFF state. A 2D Calibrated simulation study has shown an ION/IOFF ratio 105 in PD-SOI-JLT device comapred to conventional SOI-JLT device for gate length of 20 nm. Further, the use of PN junction isolation reduces the lateral electric field and hence improves the SCE performance of the proposed device as compared to conventional SOI-JLT. Besides this, the ac analysis has shown that the transconductance and Cutoff Frequency of the proposed device is at par with the conventional device. [ABSTRACT FROM AUTHOR]

In the present article, the modeling of subthreshold current of asymmetric silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) is done. The switching properties are further investigated by formulating the subthreshold swing characteristics based on the minimum potential concept. The model adopts the effect of substrate-induced surface potential (SISP) effect as well as source/drain depletion region with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. The developed model is beneficial for the optimization of low power switching characteristics for SOI JLFETs. The model results are validated with the numerical simulation results obtained from Sentaurus TCAD simulator. [ABSTRACT FROM AUTHOR]

The present paper presents a graded channel NWFET using a doping-less technique with a core gate covering the channel and drain region. The graded channel and inner gate further suppresses the short channel effects and enhances the device performance capabilities. The performance metrics of the aforementioned device are calculated and compared with Charge Plasma and junctionless GAA-NWFET. The results show that our proposed structure exhibits improved Ion, Ioff, subthreshold slope (SS) and drain induced barrier lowering (DIBL). The graded channel has been effectively created by means of the charge plasma technique inorder to decrease the fabrication cumbersomeness. To enhance the channel controllability further, using an inner gate is proposed. Our proposed device aims at making MOSFET more striking to carry on with the scaling trends. [ABSTRACT FROM AUTHOR]

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model. [ABSTRACT FROM AUTHOR]

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed. [ABSTRACT FROM AUTHOR]

The sensitivity of the hydrogen gas detector can be improved by using the extended-gate technique in nanowire FET. A ZnO-based extended-gate gate-stack junctionless nanowire field-effect transistor (EG-GS-JLNWFET) hydrogen gas device is considered for the first time in this work. Catalytic gate metal, palladium (Pd) on high-K dielectric reduces the overall work function; the concept is further used in sensor design. The presence of gate stacking and extended-gate structure together improve the gate controllability, which results in an improved current ratio. Sensitivity parameters, S I ON and S I OFF are considered for performance analysis. Results are compared with JLNWFET. The gate-stack junctionless nanowire field- effect transistor (GS-JLNWFET) shows enhancement compared to both the sensitivities in the proposed device. When compared to JLNWFET-based sensor, EG-GS-JLNWFET shows 2.59% and 24.85% improvement, respectively, in the sensitivity with respect to IOFF and ION for a change of 160 meV in the work function of palladium (Pd). Leakage in any device must be as low as possible, as it lowers the standby power losses in the device. In this work, the proposed design has lowered the leakage as compared to the rest of the two structures. The results also show an augmentation in sensitivity with the increase in gate material work function [ABSTRACT FROM AUTHOR]

In this study, Trigate Junctionless FET device has been explored for its analog performance. The anolog and RF parameters for device performance like trans-conductance (gm), output conductance (gd), intrinsic gain (Av) and cut-off frequency (ft) are evaluated using visual TCAD tool. Simulation result reveals that a very low capacitance value (in the order of 10 - 19 ) which minimises ON state delay and making the device suitable for fast switching applications. The AC analysis of device demonstrates quite high cut off frequency of 2.44 GHz and a remarkable transconductance (Gm) of 0.154 μ S. Furthermore, a novel CMOS Inverter has been designed using TGJLFET device structure in NMOS and PMOS configuration. The DC and transient response of the same has been studied extensively. [ABSTRACT FROM AUTHOR]

The silicon nanotube field effect transistor (FET) is a tubular structure and has an inner gate and outer gate to control the channel. In this paper, the performance of a junctionless silicon nanotube FET is optimized using inner and outer gate engineering through 3D numerical TCAD simulations. The performance of the optimized devices is enhanced in terms of ON current (ION), OFF current (IOFF), and I ON I OFF ratio. Appropriate work function and gate dielectric choices are suggested for the inner and outer gates to obtain optimized devices. The lowest IOFF and highest I ON I OFF ratio are obtained for devices with high inner and outer gate permittivity along with low inner and outer gate work function. Also, the highest ION is obtained for the device with the highest inner and outer gate dielectric permittivity with low outer and inner gate work function. The device optimized for ION (98.6% increase compared to reference device) with the corresponding IOFF better than the reference device can be used for high-power applications. [ABSTRACT FROM AUTHOR]

As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless accumulation-mode MOSFET (Cyl-JLAM MOSFET) to analyse its behaviour in the subthreshold region. The two-dimensional Poisson equation is solved to develop the analytical model by approximating the potential profile along the channel to be parabolic. We have formulated the expression for potential at the centre and electric field along the channel from the developed model. The key performance factors of SCEs including threshold voltage (VTH) roll-off, drain-induced barrier lowering and subthreshold slope are explored with respect to the geometry of the device parameters, i.e. body thickness of the cylindrical silicon pillar, length of the channel and thickness of the oxide layer. The results of our model are in good agreement with numerical simulations. The TCAD ATLAS 3D device simulator accounts for all the physical models required during the simulation. In this paper, the simple and distinctly formulated analytical model supports the application of the Cyl-JLAM MOSFET in integrated circuit design and optimization. [ABSTRACT FROM AUTHOR]

In this work, inclusion of high-k spacer on symmetric underlap S/D junctionless silicon nanowire (SiNW) MOSFET is studied with an aim to analyze more realistic estimation of device performance in sub-20 nm. Comparison made with junctionless silicon nanowire shows that underlap high-k spacer significantly reduces off-current (≈ 64 mV/decade) and achieves high switching ratio > 109 due to fringing field which tends to increase effective channel length. Variation of different high-k spacer values (k = 3.9, 9.1, 11, 25, and 40) is examined and following static and Analog/RF performance is studied: potential, electric field, band diagram, transconductance, device efficiency, quality factor, capacitances, cutoff frequency (fT), intrinsic delay (τ), TFP, EDP, and GBP. It is observed that for high k = 40 (TiO2), device performance of junctionless SiNW MOSFET improves noticeably in comparison to low-k value. In addition, variation of S/D underlap spacer length (Lsp) along with spacer dielectric has also been done and results reveal that TiO2 with 10 nm spacer length is optimum value for upgraded analog/RF performance. Thus, symmetric S/D underlap junctionless SiNW MOSFET can be considered as a promising component in low-power switching component in RFIC circuits. [ABSTRACT FROM AUTHOR]

In this work, a junctionless silicon nanotube TFET (JL-SiNT-TFET) is reported for low standby power and high-frequency applications. The workfunction of the core gate (CG) metal is considered similar to the outer gate electrode. The length of the CG is extended up to the source region and connected to the gate supply voltage. The inclusion of the CG offers better electrostatic controllability and enables a steep turn on capability. While maintaining low IOFF and targeting the optimum performance of the device, the JL-SiNT-TFET shows 19.8 mV/dec subthreshold swing (SS), ultra-low OFF-state leakage current, higher drive current as compared to the junctionless silicon nanowire TFET (JL-SiNW-TFET). However, temperature and substrate doping effect on device performance, core gate position optimization, the impact of channel length variation on SS, ION/IOFF ratio, and RF parameters are also investigated for choosing the most favorable values. [ABSTRACT FROM AUTHOR]

Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher Ids, gm, gd and fT compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing ION/IOFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (Rch), advanced early voltage (VEA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S21 and S12) and reflection coefficients (S11 and S22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs. [ABSTRACT FROM AUTHOR]

In this paper, we report a junctionless FinFET-based capacitor less dynamic memory by using three-dimensional technology computer-aided design simulations. To realize the 1T-DRAM, the proposed device has been designed as a structure in which a poly-si layer is deposited on the fins of a typical junctionless FinFET. Poly-si has one or more grain boundaries (GB). A GB contains multiple traps, and these traps generally degrade device performance. Also, when poly-si is grown and utilized in semiconductor devices, non-uniform GB is formed across the entire wafer. Therefore, devices manufactured using poly-si have different GBs for each device and the performance of devices fabricated on the same wafer is different. Therefore, it is essential to design a device that can operate normally regardless of GB. The 1T-DRAM proposed in this study was simulated with the existence of GB and the direction of GB differently. Finally, a device that operates normal memory regardless of GB was designed. According to the simulation results, the retention time of the proposed 1T-DRAM has a margin of more than 10 uA/um and a retention time of more than 64 ms, regardless of the presence or absence of GBs. [ABSTRACT FROM AUTHOR]

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET. [ABSTRACT FROM AUTHOR]

This paper offers the study of the noise performance of four devices namely junctionless dual-gate FET (JL-DGFET), junctionless nanowire FET (JL-NWFET), charge-plasma based dopingless dual-gate FET (DL-DGFET) and dopingless nanowire FET (DL-NWFET). This work examines the maximum Noise-Figure (NFmax.), Auto-correlation factor (< V1·V1* >)/(< V2·V2* >), cross-correlation factor (< V1·V2* >), and output impedance (real Zo). To understand the performance of devices, analog characteristics of all four devices and effect on these characteristics with the variations of different device structure parameters are analyzed and compared. Internal physics of device is understood by device design parameters such as electric field, channel potential, carrier mobility and carrier concentration. It is observed from the simulated results that JL-DGFET has better noise performance, highest ION/IOFF current ratio than other devices. [ABSTRACT FROM AUTHOR]