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We consider a two-stage manufacturing system composed of a batch processor and its upstream processor. Jobs exit the upstream processor and join a queue in front of the batch processor, where they wait to be processed. The batch processor has a finite capacity Q, and its processing time is independent of the number of jobs loaded into the batch processor. In certain manufacturing systems (including semiconductor wafer fabrication), a processing time window exists from the time instance the job exits the upstream processor till the time instance it enters the batch processor. If a job is not processed before reaching the end of its processing time window, job rework or validation is required. We model this drawback by assigning a reward R for each successfully processed job by the upstream processor, and a penalty C for each job that reaches the end of its processing time window without being processed by the batch processor. We initially assume an infinite job source in front of the serial processor and also assume that the batch processor is operated under a threshold policy. We provide a method for controlling the production of the serial processor, considering the processing time window between the upstream processor and the downstream batch processor. We then show how the serial processor control policy can be modified when the serial processor also experiences intermittent job arrival.

In this paper, we study the minimization of variance of cycle times in a dynamic single machine system where jobs arrive continuously over time. Numerous production systems give rise to single machine models, and a multiple-machine environment where the performance of a bottleneck machine determines the performance of the entire system reduces to a single machine problem [16]. Minimizing cycle time variance helps in safe predictions of the completion of job production and thus in providing the same quality of service to the customers. This allows an improved ability to meet the due dates reliably, and thus the greater coordination with further downstream operations on the jobs, as highly preferred in semiconductor manufacturing. Scheduling the bottleneck process to minimize the time of presence of the jobs in process minimizes the deterioration of cycle time-related performance measures. Low values of cycle time-related measures are also preferred for low risk of wafer contamination associated with it during processing. New scheduling rules are developed to minimize both the cycle time variance and the maximum cycle time for single machine system, wherein the machine/process is always utilized to the maximum extent and in the extreme case is heavily loaded with jobs for processing. The performance of the proposed rules is compared with the rules available in the literature and the results are presented for the objectives of minimizing cycle time variance and maximum cycle time at higher levels of machine utilization.

This paper addresses a specific class of scheduling parallel batching problem, which is observed in steel casting industries. The focus of this research is to minimize the total weighted tardiness on heterogeneous batch processing machines under conditions of dynamic job arrivals, incompatible job families and non-identical job sizes. This type of parallel batching problem arises in a number of different settings, including diffusion in wafer fabrication, heat treatment operations in aircraft industries, and metal working. The problem is viewed as a three stage-decision-problem: the first stage involves selecting a machine from the heterogeneous batch processing machines for scheduling; the second stage involves the selection of a job family from the available incompatible job families; and the third stage involves the selection of a set of jobs to create a batch from the selected job family based on the capacity of the selected batch-processing machine. Since the problem is NP-hard, a few greedy heuristics are proposed. The computational experiments show that the proposed greedy heuristic algorithms are capable of consistently obtaining near-optimal solutions (statistically estimated) in very reasonable computational time on a Pentium III 650 Mz with 128 MB RAM.

This paper presents a brief review on job shop scheduling techniques in semiconductor manufacturing. The manufacturing environment in a semiconductor industry is considered a highly complex job shop, involving multiple types of work centers, large and changing varieties of products, sequence-dependent setup times, reentrant process flow, etc., in a dynamic scheduling environment. Due to the stubborn nature of the deterministic job shop scheduling problem itself, many of the solutions proposed are of hybrid construction cutting across the traditional disciplines. The problem has been investigated from a variety of perspectives resulting in several analytical techniques combining generic as well as problem-specific strategies. In this paper, we seek to provide a brief overview of the problem, the techniques used and the researchers involved in solving this problem.

To deal with today’s stiff competition in the logistics of semiconductor manufacturing, the development of an efficient scheduling approach for the complex semiconductor back-end testing operations is very essential, where more than one objective, such as cycle time, machine utilization and due date accuracy are kept in the focus to various degrees simultaneously. In this paper, the problem of scheduling N independent jobs on a single testing machine with due dates and sequence-dependent setup times is addressed, where the multiple objectives are to minimize average cycle time and average tardiness and to maximize machine utilization. A near optimal solution, which is not inferior to any other feasible solution in terms of all objectives, is generated combining the analytically optimal and conjunctive simulated scheduling approach. First, the machine-scheduling problem is modeled using the discrete event simulation approach and the problem is divided into simulation clock-based lot selection sub-problems. Then, at each decision instance in simulated time, a Pareto optimal lot is selected using the compromise programming technique for multi-objective optimization. With the help of a broad experimental design, this developed solution is then compared with common heuristic-dispatching rules used in industry such as the shortest processing time (SPT) and earliest due date (EDD). The developed scheduling method shows better results for all the objectives over a wide range of problems. It shows approximately 16.7% reduction in average cycle time, 25.6% reduction in average tardiness, and 21.6% improvement in machine utilization over the common dispatching rules, SPT and EDD.

The scheduling of highly complex job shops, such as those found in semiconductor manufacturing, involves multiple types of work centers, large and changing varieties of the products, sequence dependent set up times, reentrant process flow, dynamically changing environment, etc. These complexities make the job shop scheduling problem very strongly nondeterministic polynominally (NP)-hard and intractable to solve by the traditional scheduling approaches. This paper presents the concept and applications of the conjunctive simulated scheduling (CSS) approach, which incorporates the benefits of discrete event simulation in scheduling the shop and avoids the NP-hard formulation of these complex scheduling problems. The differences between CSS and typical simulation studies and its application to online simulation are also presented.