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In this paper, the injection-locked oscillator (ILO)-based receiver is investigated. The key design considerations of the ILO including the phase difference between the input and output signals and its impact on the ILO-based receiver are analysed in detail. Different strategies for both the narrow and wide-band applications are discussed and simulated. As a design example, a 2.4 GHz ILO-based receiver is implemented using a standard 40 nm CMOS technology, where a three-stage inverter-based ILO is optimised to maintain a good balance among working range, sensitivity and power consumption, etc. Measurement results show that the proposed receiver is able to demodulate an input signal at a 2.4 GHz carrier frequency with the data rate up to 1 Mbps while consuming $${

Nowadays digital radio systems are replacing analog radio systems. In this paper, a CMOS RF receiver with frequency synthesizer and analog baseband is introduced, which was fabricated with a 0.18-µm CMOS process for DRM/DAB wideband applications. In the system, a fully differential low noise amplifier with a noise cancelling technology is adopted It has achieved a gain of 11.69 dB. A harmonic rejection mixer was implemented to realize the rejections of 3rd- and 5th-order harmonics. As the local oscillator, a wide-band frequency synthesizer provides a phase noise of ?125 dBc/Hz at 1-MHz offset. The designed RF receiver has achieved a conversion gain of 90 dB. The IIP3 of the receiver is in the range of ?25 to ?12 dBm, and the noise figure of 5.44---14.72 dB. The core circuits draw a current of 78.35 mA from a 1.8-V power supply and the chip occupies 6.46-mm2 die area.

The Radio Receiver Instrument (RRI) is a four-channel digital receiver fed by four 3-metre monopoles, arranged in a crossed configuration, each connected to a high input impedance preamplifier. The RRI bandwidth extends from 10 Hz to 18 MHz. The receiver measures the electric fields of either spontaneous radio emissions or waves created by ground transmitters, such as ionosondes, high-frequency radars and ionospheric heaters. In order to measure accurately the intensity, frequency, direction of propagation and signal delay of such fields over the broad frequency range, modern digital receiver technology is employed. The amplified signals from the monopoles are digitized at a rate of 40 megasamples per second, and from there on, the signal is down-converted, filtered, time-stamped and communicated in digital form. The characterization results of the RRI flight model are reported. Formats for data commands for configuring the digital receiver and for data output are described.

In this article, a novel tunable, blocker and clock jitter tolerant, low power, quadrature phase shift frequency selective (QPS-FS) receiver with energy harvesting capability is proposed. The receiver’s design embraces and integrates (i) the baseband to radio frequency (RF) impedance translation concept to improve selectivity over that of conventional homodyne receiver topologies and (ii) broadband quadrature phase shift circuitry in the RF path to remove an active multi-phase clock generation circuit in passive mixer (PM) receivers. The use of a single local oscillator clock signal with a passive clock division network improves the receiver’s robustness against clock jitter and reduces the source clock frequency by a factor of N, compared to PM receivers using N switches (N≥4). As a consequence, the frequency coverage of the QPS-FS receiver is improved by a factor of N, given a clock source of maximum frequency; and, the power consumption of the whole receiver system can eventually be reduced. The tunable QPS-FS receiver separates the wanted RF band signal from the unwanted blockers/interferers. The desired RF signal is frequency down-converted to baseband, while the undesired blocker/interferer signals are reflected by the receiver, collected and could be energy recycled using an auxiliary energy harvesting device.

A 433 MHz ?104 dBm OOK/ASK receiver with offset-peak-detecting demodulation technique has been proposed and implemented in 0.18-µm CMOS process in this paper. The offset-peak-detecting technique enhances the receiver robustness under the existence of interferences and thus improves the sensitivity. This technique also guarantees a prompt setting process of the data slicer. A passive-mixer based front-end with low noise figure and high conversion gain is employed in the receiver to reduce the noise figure. The LO signal is generated by a 433 MHz SAW oscillator. An active balun is used to convert the single-ended LO signal to differential signal which is necessary for the performance of the mixer. The receiver achieves a sensitivity of ?104 dBm and a dynamic range of 95 dB at the data rate of 20 kbps. The receiver consumes a quiescent current of 4 mA under the supply voltage from 2.1 to 3.3 V.

For the development of highly integrated, flexible and low-cost cognitive radio (CR) devices, simple transceiver architectures, like direct-conversion receiver, are expected to be deployed and provide viable radio frequency (RF) spectrum sensing solutions for practical implementation. Yet, this can be very challenging task especially if spectrum sensing and down-conversion are conducted over multiple RF channels simultaneously for improved efficiency in channel scans. Then, the so-called dirty RF problem that degrades link performance of traditional transmission systems starts to be influential from spectrum sensing perspective as well. The unavoidable RF impairments, e.g., oscillator phase noise in direct-conversion receiver, could generate crosstalk between multiple channels that are down-converted simultaneously, and thus considerably limit the spectrum sensing capabilities. Most of the existing spectrum sensing studies in literature assume an ideal RF receiver and have not considered such practical RF hardware problem. In this article, we study the impact of oscillator phase noise on energy detection (ED) based spectrum sensing in multi-channel direct-conversion receiver scenario. With complex Gaussian primary user (PU) signal models, we first derive the detection and false alarm probabilities in closed-form expression. The analytical results, verified through extensive simulations, show that the wideband multi-channel sensing receiver is very sensitive to the neighboring channel crosstalk induced by oscillator phase noise. More specifically, it is shown that the false alarm probability of multi-channel energy detection increases significantly, compared to the ideal RF receiver case. The exact performance degradation depends on the power of neighboring channels as well as statistical characteristics of the phase noise in the deployed receiver. In order to prevent such performance degradation in spectrum identification, an enhanced energy detection technique is proposed. The proposed technique calculates the leakage power from neighboring channels for each channel and improves the sample energy statistics by subtracting this leakage power from the raw values. An analytical expression is derived for the leakage power which is shown to be a function of power spectral levels of neighboring channels and 3-dB bandwidth of phase noise process. Practical schemes for estimating these two quantities are discussed. Extensive computer simulations show that the proposed enhanced detection yields false alarm rates that are very close to those of an ideal RF receiver and hence clearly outperforms classical energy detection.

Impulse radio is a low-complexity ultra-wideband system which is suitable for highly dispersive multipath channel. In this paper, we propose a random correlation-based receiver for impulse radio communications. The proposed receiver correlates the received pilot symbols with the randomly generated base functions according to channel statistics and forms the detection template by combining several base functions which have larger correlation coefficients with the pilot symbols. The proposed receiver demodulates the received signal by employing a symbol rate sampling. Computer simulation results have shown that the proposed receiver outperforms the conventional correlator-based receiver, compressive sensing correlator-based receiver, weighted energy detector and autocorrelation receiver.

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1---10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1---10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm2 including the bond pads.

A 0.1---4 GHz software-defined radio (SDR) receiver with reconfigurable 10---100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm2. The receiver achieves S11 input matching below ?10 dB and a NF of 3---8 dB across the 0.1---4 GHz range, and a maximum gain of 82---92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.

The paper analyses performances of the two lowest data rates of impulse-radio ultra-wideband DPSK physical layer of recently published IEEE 802.15.6 Body Area Networks standard. Two receiver architectures suitable for the reception of symbols with signal structure described in specification of this physical layer, namely duty-cycled sampling receiver and chirp receiver, are introduced. Then, performance of these receiver architectures are analyzed through probabilities of error in different phases of packet reception. Analysis has been performed in the presence of different types of interference; namely frequency modulated ultra-wideband, WiMax and other co-located IEEE 802.15.6 impulse-radio ultra-wideband devices.

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 µm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and ?2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.

This paper presents an RF receiver of zero-Intermediate Frequency (IF) architecture for Cognitive Radio (CR) communication systems. Zero-IF architecture reduce the image reject filter and IF filter, so it is excellent in low cost, compact volume, and low power dissipation. The receiver employs three digital attenuator and a high gain, high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of −81 dBm. A fully balanced I/Q demodulator and a differential Local Oscillator (LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage. In order to select an 8 MHz-channel from 14 continuous ones located in UHF band (694–806 MHz) accurately, approach of channel selectivity circuits is proposed. The RF receiver has been designed, fabricated, and test. The measured result shows that the noise figure is 3.4 dB, and the error vector magnitude is 7.5% when the input power is −81 dBm.

This paper proposes a one-branch zero-IF receiver topology, which samples the I and Q signals of the modulated RF carrier with one signal path by means of a multiphase local oscillator. The suggested one-branch receiver works without matching problem, and it is also capable of cancelling out the flicker noise and DC-offset when the local oscillator is configured to the four-phase mode. The one-branch receiver saves much area and power compared with the traditional two-branch ones. All of the advantages above make the one-branch receiver topology a promising architectural candidate for low-power and low-cost RF CMOS receiver designs.

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of ?95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of ?76 and ?79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.

This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 μm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (Gm-LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed Gm-LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I---V, V---I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred third-order intercept point (IIP3) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.

In this article, two issues pertaining to MRI digital receivers are addressed. One is the maintenance of phase coherence between the transmitter and the receiver—an effective solution is proposed, in which the receiver frequency is switched synchronously with the transmitter frequency. The other is the dynamic range of the receiver—gain-switching technique is utilized to improve the dynamic range. To meet the hardware requirements of these solutions, a digital receiver with fast frequency- and gain-switching capabilities was implemented. The primary components of the proposed digital receiver are a variable gain amplifier, a high-speed analog-to-digital converter and a single-chip digital receiver core. The radio-frequency magnetic resonance signal is directly sampled by the analog-to-digital converter and processed in the digital receiver core. By pre-storing the receiver waveform in the on-board SDRAM, the frequency and gain of the receiver may be switched very quickly. The performance of the proposed digital receiver is verified by embedding it in an imaging spectrometer. It is then demonstrated by conducting experiments on a home-built 0.3-T magnetic resonance imaging system. The results show that the phase coherence between the transmitter and the receiver and the dynamic range of the receiver are greatly improved. Consequently, the proposed digital receiver may be useful for obtaining multiple-slice two-dimensional magnetic resonance images with very high resolution.

The requirements imposed on the parameters of frequency filtering and the level of test signals, and also on the screening of the measuring apparatus, are substantiated.

In this paper, based on analyses of the Chinese Area Positioning System (CAPS) satellite (GEO satellite) resources and signal properties, the signal power at the port of the receiver antenna is estimated, and the implementation projects are presented for a switching band C to band L CAPS C/A code receiver integrated with GPS receiver suite and for a CAPS dual frequency P code receiver. A microstrip receiving antenna is designed with high sensitivity and wide beam orientation, the RF front end of the C/A code and P code receivers, and a processor is designed for the navigation baseband. A single frequency CAPS C/A code receiver and a CAPS dual frequency P code receiver are built at the same time. A software process flow is provided, and research on relatively key techniques is also conducted, such as signal searching, code loop and carrier loop algorithms, a height assistant algorithm, a dual frequency difference speed measurement technique, a speed measurement technique using a single frequency source with frequency assistance, and a CAPS time correcting algorithm, according to the design frame of the receiver hardware. Research results show that the static plane positioning accuracy of the CAPS C/A code receiver is 20.5–24.6 m, height accuracy is 1.2–12.8 m, speed measurement accuracy is 0.13–0.3 m/s, dynamic plane positioning accuracy is 24.4 m, height accuracy is 3.0 m, and speed measurement accuracy is 0.24 m/s. In the case of C/A code, the timing accuracy is 200 ns, and it is also shown that the positioning accuracy of the CAPS precise code receiver (1 σ) is 5 m from south to north, and 0.8 m from east to west. Finally, research on positioning accuracy is also conducted.

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5-6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 µm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

System co-optimization of the analog receiver front end circuit and the digital baseband processing could enable receiver designs with lower power budgets, as the signal processing in the digital receiver is asymmetric across circuit topologies. This paper presents a simulation tool that could assist with such co-optimized designs. TrACS (Transceiver Architecture and Channel Simulator) is an RF/DSP co-simulator, capable of providing an application-specific system-level perspective to receiver design. The simulator is especially relevant in the context of energy-constrained wireless sensor node design, where the simulator's system perspective determines the compatibility of circuit topologies, modulation techniques and synchronization methods for various wireless scenarios. A few case studies are presented, which illustrate co-optimization of a ZigBEE receiver using TrACS. QC 20100525

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point $$(P_{{-1}\,{\rm dB}})$$ of ?13.5 dBm and the input-referred third-order intercept point (P IIP3) of ?1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of $$1.45 \times 0.72$$ mm2 including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.

This paper investigates three decision- feedback receivers for Direct-Sequence Ultra-Wideband Radio (DS-UWB) based on two-channel BPSK modulation with ternary spreading code. A compact and insightful vector-matrix signal model is built up for receiver design under UWB channel dispersion over many consecutive symbols. First, we consider the design of a RAKE with Decision Feedback (RAKE-DF) receiver. Using the Gaussian approximation technique, we derive its analytic performance under no error propagation. It is shown that the RAKE-DF receiver suffers from a significant error floor due to the uncancelled pre-cursor ISI (or pre-ISI abbreviated). Next, we design the MMSE-DF receiver to achieve a better performance by suppressing the pre-ISI, too. However, the MMSE receiver requires costly matrix inversion. Then a new receiver is investigated as the third one, which is called the RAKE with Bi-Directional Decision Feedback (RAKE-BDDF) receiver, for efficiently canceling both the post-(cursor) ISI and pre-ISI at symbol rate. It cannot only attain the matched filter bound approximately, but also maintain a similar complexity as that of the RAKE-DF receiver. Simulation and semi-analytic BER curves are included for performance comparison of the three receivers in the presence of the CM2 and CM4 UWB channels.

This paper proposes a cost-effective CMOS optical receiver with a level shifter to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. In this design, a level shifter is introduced at the receiver, in order to improve digital audio quality by threshold convergence. Measurement results demonstrate that the implemented optical receiver in a 0.25-μm CMOS technology can successfully reduce pulse width distortion within ?2% and circuit complexity.

Impulse Radio (IR) modulation is perceived to be a practical means of exploiting the multi-gigahertz bandwidth available for UWB links. However, the RMS delay spreading of indoor channels relative to the transmitted pulse width is typically very large such that several hundred signal samples are required to be quantized and processed for each received pulse. To realize a relatively low power low-complexity receiver of satisfactory performance in low signal to noise ratio environments, signal sampling based on single bit quantization is proposed which is readily realizable at gigahertz rates with modest power consumption. In this paper, the architecture and performance of a coherent IR receiver based on single bit quantization will be analyzed from the perspectives of Rake receiver processing, channel estimation and signal detection. This paper demonstrates that single bit quantization results in a modest manageable performance penalty relative to linear multi-bit sampling. This penalty is readily justifiable in light of the significant reduction in overall receiver complexity.

The frequency channelized receiver enables the use of practical analog-to-digital converters (ADC) to digitize ultra-wideband (UWB) signals. The design issues of the analog and digital baseband processor for the channelized receiver in a UWB transmitted reference (TR) system are investigated. In the analog part, the receiver performance is shown to be weakly dependent on the analog filter bandwidth, the filter order, and the ADC oversampling ratio assuming white input noise. In the digital part, the coarse acquisition performance is shown to be significantly better in a channelized receiver than in a fullband receiver. The implementation issues for fine synchronization and correlation window length are also studied.

The compensation of radio interference, which penetrates through the screen of a measuring receiver is considered, and it is shown that it is possible to extend the dynamic range when measuring electromagnetic compatibility characteristics.

We have built a 100 GHz sideband-separating receiver. The receiver, a breadboard for the band 3 cartridges for ALMA, achieves a SSB noise temperature of 6hf/k with a 4–8 GHz IF. We show that it is possible to meet the ALMA specifications. The design of the receiver is reviewed and the relationships between the receiver noise temperature and properties of the components used in the receiver are discussed.

This paper proposes a novel zero Intermediate Frequency (IF) receiver for Multi-Carrier (MC) Direct-Sequence Code-Division Multiple Access (DS-CDMA) based on multicarrier mode of cdma2000 system. The proposed receiver employs direct RF-to-baseband down-conversion, sampling at a rate equal to the bandwidth of the baseband multicarrier signal and complex-valued coefficient FIR filters. This receiver avoids the need for arrays of high Q analog bandpass filters, has a much lower sampling rate half of that of conventional receiver and offers significant savings in hardware implementation. Analytic and simulation results show that the presented receiver performs well for both the AWGN channel and Rayleigh fading channel.

This paper concerns the design, the implementation and the validation of a fully integrated front-end receiver for a portable ultrasonic system. This front-end receiver includes a logarithmic preamplification circuit and followed by a programmable-gain compensator. The proposed building blocks largely amplify small amplitude signals, and moderately the large amplitude ones. They also compensate signal attenuation due to its traveling of several human body tissues. The ultrasonic receiver is implemented in CMOS 0.35 μm technology. Spectre simulations of the front-end receiver show unity gain bandwidth higher than 100 MHz when driving a load of 1 pF. The expected measurements of the fabricated chip are reported. This chip operates at 3.3 V supply voltages, while maintaining wide common mode rejection ratio, high gain and low input offset voltage. The total power consumption is 15.6 mW and the total chip area is 7.2 mm2 including the digital part needed to program the TGC.

We have developed a 3 mm band receiver for SRAO. The receiver employs an Nb-based SIS junction in the mixer and operates at 85–115 GHz with single polarization. The receiver noise temperature is 40–50 K in DSB. It is equipped with an MPI-type filter for single-side band observations. We present the design, construction, and test results for individual components of the receiver optics, heterodyne system, and cryogenics. The receiver has been installed on the 6 m SRAO telescope and tested toward astronomical sources. The beam-measurement experiment suggests that the edge taper is smaller than the designed 12 dB.

In this paper, the blocking effect that takes place in MM-wave receiver is analyzed; the methods that prevent and avoid the blocking effect are put forward. The results analyzed and the methods put forward possess certain useful significance for many MM-wave receivers in which the RF amplifiers are contained at present.

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal–oxide–semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal. Graphene transistors are attractive for many applications but making integrated circuits without degrading their characteristics is proving challenging. Here, the authors demonstrate a radio frequency integrated receiver using a graphene-last approach compatible with conventional processing methods.

We describe the design of a superheterodyne receiver with a balanced monolithic integrated mixer and describe the technique and results of parameter measurements of the receiver and mixer over the frequency range 287–365 GHz. In the middle of this range, the double-band noise temperature of the receiver is 1500±50 K, while the double-band noise temperature and conversion loss of the mixer are 1250±50 K and 10±0.5 dB, respectively. Comparison with mixers and receivers of other types is performed.

An implementation of a reverse link receiver for IS-95 CDMA (Code-Division Multiple-Access) communications that applies decision feedback to the decoding of the received signal is presented. Decision feedback is used in order to improve BER performance by making use of additional information that conventional receiver designs generally ignore. Qualitative analysis and computer simulation of the hardware components of the proposed implementation shows that it can be built as a single integrated circuit using present day technology. The design presented here does not include the RF front-end of the receiver, does not consider the effects of multipath and fading on system performance, and assumes perfect power control.

Smart antennas for base stations of cellular mobile radio systems offer the potential of system performance enhancement by taking advantage of the directionally inhomogeneous signal reception at the receiver. In this paper, two-dimensional array configurations employed at the uplink receiver of a joint detection CDMA (JD-CDMA) mobile radio system are investigated. This smart antenna concept can be split up into a novel channel estimator and data detector which incorporate explicitely the information of the direction-of-arrival (DOA) of signals emerging from users assigned to the considered base station. Proceeding from channel models that model the directional inhomogeneity of the mobile radio channel with single DOAs, the link level performance of a JD-CDMA mobile radio system using this smart antenna concept is evaluated for the rural propagation environment. The performance evaluation is based on Monte Carlo simulations of data transmission and average bit error rates versus the average signal to noise ratio per net information bit are presented for different array configurations. Although these results should be considered as upper bounds for the link level performance, they reveal the advantages of implementing two-dimensional array configurations at the uplink receiver of a JD-CDMA mobile radio system.

The integration of many receiver units into a receiver array is a common method of improvement of imaging systems. This approach, well known in the mm band for Schottky mixer arrays, has not so far been developed for Superconductor - Insulator - Superconductor (SIS) junction mixers, which give the best sensitivity in the short mm wave range and in the submm range. We demonstrate for the first time a practical low noise multibeam receiver module using SIS mixer technology. The basis for the integration of several SIS mixers with a common local oscillator source is given by the saturation of the SIS receiver noise dependence upon local oscillator power. The module comprises three identical SIS mixers integrated with a common local oscillator, coupled through a three branch waveguide directional coupler. The multibeam module has been developed for a focal plane array receiver of the 30 meter radio telescope of the Institut de Radioastronomie Millimetrique (IRAM).

We present the design and experimental data of an SIS waveguide mixer for frequencies from 760 to 820 GHz. We use a Nb-Al2O3-Nb junction with an integrated niobium tuning structure. The waveguide mixer block contains no adjustable tuning elements. Design criteria for lossy tuning structures, differing from the impedance matching techniques used in the lossless case, are described. We separate the influence of the intrinsic mixing properties of an SIS junction from the effects of the power coupling to the signal source on the overall noise. This allows us to derive the contributions of the optics, the losses in the stripline and the noise generated in the junction to the total receiver noise from the measurements. We achieve double sideband receiver noise temperatures of around 850 K at frequencies from 780 to 820 Ghz and 4.2 K operating temperature of the mixer. Cooling the mixer to 2.5 K results in an improvement of the receiver noise temperature by 150 to 200 K. The bandwidth is presently limited by the local oscillator. The mixer was successfully used in a dual channel receiver (440 to 490 GHz and 780 to 820 GHz) at the Submillimeter Telescope Observatory (SMTO) on Mount Graham, Arizona.

A conventional angle diversity receiver uses multiple receiving elements that are oriented in different directions, where each element employs its own filter and nonimaging concentrator, such as a compound parabolic concentrator (CPC) or hemispheric lens. In this paper, a study of the design of a conventional receiver structure using angle diversity that offers improved performance with respect to the infrared channel characteristics is presented. To this end, a recently proposed model for the effective signal collection area of a conventional angle diversity receiver that more closely approximates real behaviour than the ideal model is used. The inclusion of this model in a Monte Carlo ray-tracing algorithm allows us to investigate the effects of conventional receiver parameters on the main infrared channel parameters, such as path loss and rms delay spread. Furthermore, in order to determine the number of receiver elements, the outage probability and the average error probability are also considered. Based on the results, a conventional angle diversity receiver composed of seven elements is proposed, with one of them oriented towards the ceiling, and six angled at a 56° elevation with a 60° separation in azimuth. For each element, a CPC with a 50° field of view must be used.

A new type of optical receiver design providing high sensitivity and high dynamic range is presented that employs a lossy noise-matching network and feedback type amplifier. The design is based on the noise figure concept using the four noise parameters of FET, which makes it easy to design multigigabit opical receivers by combining it with microwave CAD tools. The effects of matching network element value and group delay variation of the preamplifier on receiver sensitivities are addressed. The predicted receiver sensitivity including the effect of group delay is -27.1 dBm, which is the highest sensitivity for a 10 Gbit s-1 PIN-FET optical receiver reported to date.

The design and performance are described of an SIS waveguide receiver which provides low noise performance from 375 to 510 GHz. At its design frequency of 492 GHz the receiver has a double-sideband noise temperature of about 172 K. By using embedded magnetic-field concentrators Josephson pair tunneling is effectively suppressed. Techniques for improving receiver performance are discussed.

A 128-channel digital correlation receiver has been built for the GEETEE 1, the low-frequency radio telescope situated at Gauribidanur, South India, (latitude 13°36′12′′ N). The receiver uses a modified doublesideband (DSB) technique. The quadrature samples required for a DSB system are obtained by sampling the digitized intermediate frequency (I.F.) signals by two clocks which are separated in time by one quarter of the period of the I.F. The visibilities required for one-dimensional synthesis are measured using one-bit correlators. A technique to measure amplitude information for the signal using a threshold detector and a one-bit correlator has been developed. The receiver has been successfully used for continuum, spectral-line and pulsar observations. The antenna system of GEETEE and its configuration for one dimensional synthesis are also described in this paper

A V-band receiver using a MHMIC multiport circuit is presented in this paper. The millimeterwave frequency conversion is performed using a passive circuit, the multiport, and related power detectors, avoiding the conventional millimeter-wave active costly mixers. Basically, the multiport circuit is an additive mixer in which the resulting sum of millimeter-wave signals is nonlinearly processed using millimeter-wave power detectors. This multiport heterodyne receiver is an excellent candidate for the future low-cost high-speed millimeter-wave wireless communication systems. The operating principle of the proposed heterodyne receiver and demodulation results of high-speed MPSK/QAM signals are presented and discussed in this paper. According to suggested datarate of 100–400 Mbps used to prove the operating principle, the IF of this receiver was chosen at 900 MHz. Therefore, this receiver is a possible alternative solution for WPAN applications

High data rates, low-power consumption, and low complexity will be the most important parameters in the design of the next-generation mobile terminals. In this paper we are introducing a new paradigm in the design of direct sequence spread spectrum receiver by combining analog and digital signal processing. The main difference with respect to the conventional all-digital receiver design approach is that the proposed mixed analog/digital processing results in a symbol rate sampling rather than the high-rate subchip sampling. Analog signal despreading is the key part of the proposed receiver solution, which is based on a five-port device, a passive RF square-law-type device. It is used to perform two important tasks at the same time, namely, the direct conversion and analog despreading. To achieve lower complexity, the proposed receiver uses rectangular instead of pulse-matched despreading at the cost of only a small performance degradation. Also, we propose a new noncoherent pseudonoise (PN) code tracking scheme based on error signal generated through the L1 norm. This results in comparable or even better PN code tracking performance than L2 norm circuitry, using less complex hardware. Further, we explore how this technology can be applied in the design of DS-CDMA RAKE receiver for mobile terminals. Depending on how the pilot signal is multiplexed, we propose two types of RAKE receivers. It is shown that under Rayleigh fading channel such receiver structures offer robustness and high performance, while maintaining the low complexity achievable through the five-port device.

A simplified theory for the performance of a digital optical receiver is developed. The receiver sensitivity is calculated in terms of circuit parameters, received and equalized pulse shapes, photodiode parameters and bit-rate. An excellent agreement between this theory and a more complicated analysis by Personick [4] is demonstrated. It is shown that the receiver sensitivity may be improved by launching reduced-width pulses into the fibre, particularly if fibre bandwidth is a significant limitation. Reduced-width pulses bring benefits in source power consumption and lifetime, and in timing recovery.

This paper describes a 95 GHz receiver system based on a solid state oscillator which makes it possible to measure the electron temperature of the plasma in the tokamak TJ-1. We discuss the construction of the receiver system and its calibration, which is carried out by using a noise source in this band. The characteristics obtained for a 0,5 eV signal are presented. The results show that the receiver has a very low noise level, even for powers on the order of several picowatts.

The effects of photodiode bulk leakage current and amplifier noise on receiver sensitivity are analysed using a model described previously [4]. The sensitivity of a receiver using a PIN photodiode can be greatly improved by employing a high-performance microwave FET in the input stage, to the point where its remaining technical disadvantage in comparison with a silicon APD receiver at 800–900 nm may be offset by economic and operational attractions. In systems operating at the optimum transmission wavelength beyond 1.1 μm, the PIN-FET hybrid receiver may offer better technical performance than an APD receiver.

The equipment for determining the parameters of receivers makes it possible to select the optimum operating conditions for bolometers, i.e. to find the values of the operating current and frequency which correspond to the receiver's minimum threshold sensitivity. The use of a vibration-type modulator fed from an audio oscillator provides rapid measurements of receiver parameters in the basic range of 3–70 cps. The utilization of a phase detector in the measuring device provides a uniform bandwidth over the whole operating frequency range. The evaluation of the transfer constant under working conditions for each receiver connected to a transformer does not require additional time, but it raises the reliability of measurements.