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To meet the specification of the qubits in our laboratory, a 0.4 kA·cm−2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb-based self-aligned lift-off process. This circuit consists of a single-flux-quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T-flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He-3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ-qubit control circuits.

Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD’s jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.

Switching time limitations of the ac bias current of Josephson junctions in bidirectional rapid single flux quantum (RSFQ) logic circuits are investigated in order to determine the limits to the maximum possible operating frequency. We introduce a new approach based on modifying the bias current parameters and determining the inductance values in the circuit for reducing the switching transition time of the bias current through the junctions. We have simulated and optimized the timing and the operation of the bidirectional nondestructive readout and Josephson transmission line cells in this respect to demonstrate the results of utilizing the proposed approach. We successfully reduced the unwanted spike-type signals across the inductances which are made through the transitions during the fast switching times limiting the operation frequency. This is while we have also removed the consequent destructive spikes at the output. We have included the effects of other determining parameters of the circuit in this investigation and found their relatively optimal values to improve the temporal behavior of the bidirectional RSFQ cells. The results of the proposed approach leading to the fastest possible operation of the considered gates obtained in this work are thoroughly reported.

Rapid Single Flux Quantum (RSFQ) computing is a developing technology that enables high speed computing such as microprocessors, network routers and analog to digital converters. However, as the complexity and the computing speed of these circuits increase, timing errors of individual gates become more relevant. Most of these timing errors occur on the signal distribution path due to the use of a large number of wiring cells but these effects are mostly ignored. Hence future circuit optimization tools should take both delay and jitter amount into account. Therefore, delay and jitter values of single and cascaded fundamental RSFQ wiring cells, namely Josephson transmission lines (JTL), splitters, and mergers, are analyzed. Also, low bias voltage driving of the circuit and the dependence on input signal frequency effects are observed. In conclusion, jitter and delay values depending on the aforementioned parameters for single gates and cascaded gates are reported.

We have developed and tested a classical superconducting logic interface to a qubit prototype based on two macroscopically distinct quantum states of a vortex in a long Josephson junction. The initial state preparation as well as the readout of a qubit is demonstrated by using a relatively simple Rapid Single Flux Quantum (RSFQ) circuit. RSFQ logic appears as a very feasible choice for constructing an interface between superconducting qubits and room-temperature electronics.

The principles and characteristics of rapid single flux quantum (RSFQ) circuits are discussed. According to these theories, we have designed RSFQ inverter, XOR cell and shift registers relative to the pseudo random generator. Based on these cells, the RSFQ pseudo random generator is given. Compared with the simulation result of another mathematical model that is established by MATLAB, the design of the RSFQ pseudo random generator is proved to be reasonable and meets our expectations.

The influence of Mn substitution for Fe on the structure and magnetic properties of Pr2Fe17-xMnx compounds with 0 less than or equal to x less than or equal to 9 was investigated. X-ray diffraction indicates that all samples are single phase with the rhombohedral Th2Zn17-type structure. The unit cell volume V remains nearly constant with increasing manganese content up to x=2, then increases linearly at a rate of about 2.5 Angstrom(3) per Mn atom up to x=8 and there is a large increase of cell volume at x=9. The Curie temperature increases a little from 298 K at x=0 to 308 K at x=1, and then decreases to 37 K at x=9 quickly. The saturation magnetization at 5 K was found to decrease monotonously with increasing Mn concentration. The thermal magnetization curves M(T) of the compounds with x=1-9 show a strong decrease below T-C with decreasing temperature. Also it presents considerable magnetic hardness at low temperature. This can be attributed to the presence of narrow Bloch walls. (C) 1999 American Institute of Physics. [S0021-8979(99)05621-2].

Ramp-type Josephson junctions with YBCO superconducting electrodes and PrBa 2 Cu 2.6 Ga 0.4 O 6+δ (PBGCO) barriers were fabricated and characterized. The YBCO ramp junctions with 25 nm-thick barriers of PBGCO showed typical resistively- shunted-junction (RSJ)-like I-V behavior and 1σ spread of less than 13% in critical current density. Differential conductance-voltage characteristics registered using a lock-in technique indicate that the resonant tunneling via localized states in the barriers plays a dominant role in the conduction process of the ramp junctions.

The centers-of-gravity optimization method has been applied to optimize a complex circuit consisting of a dc/SFQ-converter and RSFQ voltage doubler in order to obtain maximum parameter margins. As a result, the margins of all circuit parameters have been enlarged to at least ±35%. This improves the yield of the circuit fabrication process. On the other hand, the upper limiting frequency and the output voltage of the circuit, respectively, are decreased by the yield optimization process.

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits. This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared. In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.

This paper gives a brief review of the Rapid Single-Flux-Quantum (RSFQ) logic family which leads the race toward practical ultrafast superconductor digital electronics, with an attempt to sketch a “roadmap” for the RSFQ technology and compare it to the renowned National Technology Roadmap for Semiconductors.

Coulomb interactions can cause a rapid change in the phase of the wavefunction along a very narrow superconducting system. Such a phase slip at the quantum level is now measured in a chain of Josephson junctions.