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This paper presents a real-time iris segmentation technique that is well suited to a fast implementation on an FPGA. One major hurdle associated with iris segmentation techniques is the use of iterative processes that lead to expensive hardware implementations. To circumvent this, the proposed algorithm uses the sign image obtained from subtracting the background, along with morphological operators to localise the pupil. The outer boundary is located by first normalising a selected image region that contains the iris, and then using a first-order gradient operator. The proposed non-iterative algorithm is implemented on an FPGA. Four near infrared (NIR) iris public databases, namely: CASIA-IrisV3-Lamp, MMU v1.0, ND-IRIS-0405 and NIST ICE 2005, are used to test the proposed algorithm. The proposed method for iris segmentation and normalization gives much better accuracy than the existing state-of-the-art methods implemented on hardware. The proposed realisation requires about 45% fewer logic registers and 52% fewer logic elements than the existing state-of-the-art implementations.

Scientists have devoted a lot of affords to guarantee the safety of cryptosystems by improving cryptography algorithms, while these systems can still be vulnerable to side-channel information analysis based on neural networks (NNs) and principal component analysis (PCA). PCA can be used as a preprocessing stage, while NNs can learn the signature (power consumption and electromagnetic emission) of an instruction of a cryptography algorithm, and then recognizes it later automatically. This paper investigate the performance of NNs as a powerful classifier to analysis the side-channel information. For this purpose, an experimental investigation was conducted based on the power consumption and electromagnetic emission analysis of a field-programmable gate array implementation of elliptic curve cryptography. In our experimental results, the performance of different NNs topologies are compared which provide useful information for cryptosystem designers. In addition an efficient NN topology is introduced for characterization of side-channel information.

Breast Cancer is a serious threat to women. The identification of breast cancer relies heavily on histopathological image analysis. Among the different breast-cancer image analysis techniques, classifying the images into Benign and Malignant classes, have been an active area of research. The involvement of machine learning for breast-cancer image classification is also an active area of research. Considering the importance of the breast-cancer image classification, this paper has classified a set of histopathological images into Benign and Malignant classes utilizing Neural Network techniques and Random Forest algorithms. As histopathological images suffer intensity variation, in this paper, we have normalized the intensity information by newly proposed intensity normalization techniques, and classify the images using Neural Network techniques and Tree-based classification tools. Investigation shows that the proposed Normalization technique gives the best performance when we use Neural Network techniques but Tree-based algorithms such as the Random Forest algorithm give better performance when we use images without normalization techniques.

Bone fracture detection from the digital image segmentation is a well-known image processing application which is frequently used to process biomedical images. Hardware realization of different image processing algorithm specially utilizing Field Programmable Gate Array (FPGA) has been gained a great interest among the researchers. FPGA has many significant features like spatial and temporal parallelism that best suits for real-time implementation of image processing. To gain the benefit from these characteristics of a FPGA, a new method for bone fracture detection is proposed and its performance is validated through real-time implementation. Simulation results show that the proposed method give superior performance than the existing method.

This article proposes a novel architecture to perform modular multiplication in the Residue Number System (RNS) by using sum of residues. The highly parallel architecture is implemented using VHDL and verified by extensive simulations in ModelSim SE. The pipelined and non-pipelined versions of the design are implemented on ASIC and FPGA platforms to allow a broad comparison. The proposed architecture requires only one iteration to complete modular multiplication and achieves 12---90 % less delay as compared to the existing RNS and binary modular multipliers. The complexity of the proposed design is also less than the existing state-of-the-art RNS-based modular multipliers. The high scalability and flexibility of the proposed architecture allows it to be used for a wide range of high-speed applications.

Traditional cryptanalysis assumes that an adversary only has access to input and output pairs, but has no knowledge about internal states of the device. However, the advent of side-channel analysis showed that a cryptographic device can leak critical information. In this circumstance, Machine learning is known as a powerful and promising method of analysing of side-channel information. In this paper, an experimental investigation on a FPGA implementation of elliptic curve cryptography (ECC) was conducted to explore the efficiency of side-channel information characterisation based on machine learning techniques. In this work, machine learning is used in terms of principal component analysis (PCA) for the preprocessing stage and a Cascade-Forward Back-Propagation Neural Network (CFBP) as a multi-class classifier. The experimental results show that CFBP can be a promising approach in characterisation of side-channel information.

Modular multiplication can be performed in the residue number system (RNS) using a type of Montgomery reduction. This paper presents an alternative in which RNS modular multiplication are performed by using the core function. All of the intermediate calculations use short wordlength operations within the RNS. This work contributes to the long wordlength modular multiplication operation $$Z = A \times B \mod M$$Z=A×BmodM, the basis of many DSPs and public-key cryptosystems.

A new algorithm for modular multiplication in the residue number system (RNS) is presented. Modular reduction is performed using a sum of residues. As all of the residues can be evaluated simultaneously, the algorithm permits a highly parallel implementation and is suitable for performing public-key cryptography operations with very low latency.