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Memristors and memristor crossbar arrays have been widely studied for neuromorphic and other in-memory computing applications. To achieve optimal system performance, however, it is essential to integrate memristor crossbars with peripheral and control circuitry. Here, we report a fully functional, hybrid memristor chip in which a passive crossbar array is directly integrated with custom-designed circuits, including a full set of mixed-signal interface blocks and a digital processor for reprogrammable computing. The memristor crossbar array enables online learning and forward and backward vector-matrix operations, while the integrated interface and control circuitry allow mapping of different algorithms on chip. The system supports charge-domain operation to overcome the nonlinear I–V characteristics of memristor devices through pulse width modulation and custom analogue-to-digital converters. The integrated chip offers all the functions required for operational neuromorphic computing hardware. Accordingly, we demonstrate a perceptron network, sparse coding algorithm and principal component analysis with an integrated classification layer using the system. A programmable neuromorphic computing chip based on passive memristor crossbar arrays integrated with analogue and digital components and an on-chip processor enables the implementation of neuromorphic and machine learning algorithms.

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

A configurable, channel-adaptive K-best MIMO detector for multi-mode wireless communications that adapts computation to varying channel conditions to achieve high energy-efficiency is presented. An 8-stage configurable MIMO detector supporting up to a 4×4 MIMO array and BPSK to 16-QAM modulation schemes has been implemented and simulated in 0.80V, 22nm Tri-gate CMOS process. Dynamic clock gating and power gating enable on-the-fly configuration and adaptive tuning of search radius K to channel response which results in 10% to 51% energy-efficiency improvement over non-adaptive K-best MIMO detectors. During unfavorable channel conditions, the MIMO detector satisfies target BER by setting K=5. For favorable channel conditions, K is reduced to 1, where 22nm circuit simulations show 68% energy reduction. At 1.0GHz target frequency, the total power consumption is 15mW (K=1) to 35mW (K=5), resulting in energy-efficiency of 14.2pJ/bit (K=1) to 44.7pJ/bit (K=5) and 3.2Gbps throughput.