Search

This paper proposes a novel method to adaptively select the best driver to load transistor fin ratio of CMOS FinFET logic inverter according to the best values of noise margins and inflection voltage with a comparison of the use of different and combined Si and Ge as a load and/or driver semiconductor channel in CMOS FinFET inverter logic circuit. The methodology of optimizing the driver to load transistor fin ratio depends strongly on improving the noise margins and inflection voltage of the output characteristics of CMOS logic inverter. The first step in this investigation of CMOS-FinFET-inverter is to obtain the output characteristics (Id-Vd) of the FinFET, and then use the MATLAB simulation model to create CMOS Fin- FET transfer characteristics. Transfer characteristics of CMOS-FinFET-logic inverter are studied with fin ratios Np/Nn of 5/1, 4/1, 3/1,2/1, 1/1, 1/2, 1/3, 1/4, 1/5. Noise margins and inflection voltage are used as critical factors to obtain the optimal fin ratio (Np/Nn). The results indicate that optimization depends strongly on the fin ratio for all combined semiconductor loads to FinFET driver inverters. The results show that the best ratios for Si:Si, Si:Ge, Ge:Si, and G:Ge are 2:1, 1:4, 2:1, and 1:3 respectively. [ABSTRACT FROM AUTHOR]

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4. [ABSTRACT FROM AUTHOR]

Among various sensing and monitoring techniques, sensors based on field effect transistors (FETs) have attracted considerable attention from both industry and academia. Owing to their unique characteristics such as small size, light weight, low cost, flexibility, fast response, stability, and ability for further downscaling, silicon nanowire field effect transistor (SiNW-FET) can serve as an ideal nanosensor. It is the most likely successor to FET-based nanoscale devices. However, as the dimensions (channel length and diameter) of SiNWT channel are shrinking down, electrical and temperature characteristics of SiNWTs should be affected, thereby degrading transistor performance. Although applications of SiNWTs as biological and/or chemical sensors have been extensively explored in the literature, less attention has been devoted to utilize such transistors as temperature sensors. Therefore, this paper characterizes the temperature sensitivity of SiNWT depending on the channel oxide thickness and also presents the possibility of using it as a nano-temperature sensor. The MuGFET simulation tool was used to investigate temperature characteristics of the nanowire. Current-voltage characteristics with different values of temperature and with different thickness of the nanowire gate (oxide thickness (TOX) = 1, 2, 3, 4, and 5 nm), were simulated. Metaloxide- semiconductor (MOS) diode mode connection was suggested for measuring the temperature sensitivity of SiNWT. Several operating voltages (0.25 to 5 V) with various working temperature (250 to 450 K) were investigated. The obtained results show that the highest temperature sensitivity was achieved by increasing oxide thickness to 5 nm. The impact of the considered temperature on SiNWT characteristics demonstrates the possibility of utilizing it as a temperature nanosensor. [ABSTRACT FROM AUTHOR]

Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors’ dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate and a successor to conventional planar devices in nanoscale technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest of researchers in both academia and industry. However, aggressively scaling down of channel dimensions, will degrade the overall performance due to detrimental short channel effects. In this paper, we investigate the impact of downscaling of nano-channel dimensions of Germanium Fin Feld Effect Transistor (Ge-FinFET) on electrical characteristics of the transistor, namely; ION/IOFF ratio, Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to conduct a simulation study to achieve optimal channel dimensions by considering channel length (L), width (W), and oxide thickness (TOX) individually. In addition, the effects of simultaneous consideration of all dimensions by exploiting a scaling factor, K was evaluated. According to the obtained simulation results, the best performance of Ge-FinFET was achieved at a minimal scaling factor, K = 0.25 with 5 nm channel length, 2.5 nm width, and 0.625 nm oxide thickness. [ABSTRACT FROM AUTHOR]