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This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature. [ABSTRACT FROM AUTHOR]

This paper deals with the bridge-style circuits. They are highly efficient in terms of transistor density per unit of area. They comply with the conventional CMOS style and form a full-swing and robust structure. First, we clarify the necessary conditions under which a Boolean function can be implemented fully symmetrical. Then, it is demonstrated that it is possible to design out of functions fully symmetrical. Eventually, we show how the pull-up and pull-down networks are constructed in a bridge circuit for any three-input function which fulfils the conditions of being implemented fully symmetrical. [ABSTRACT FROM AUTHOR]

As computation costs increase to meet design requirements for computation-intensive graphics applications on today's embedded systems, the pressure to develop high-performance parallel processors on a chip will increase. Acceleration of the ray tracing computation has become a major issue as the computer graphics industry demands for rendering realistic images. Network-on-chip (NoC) techniques that interconnect multiple processing elements with routers are the solution for reducing computation time and power consumption by parallel processing on a chip. It is also essential to meet the scalability and complexity challenges for system-on-chip (SoC). In this article, we describe a parallel ray tracing application mapping on a mesh-based multicore NoC architecture. We describe an optimised ray tracing kernel and parallelisation strategies, varying the workload distribution statically and dynamically. In this work, we present results and timing performance of our parallel ray tracing application on a NoC, which are obtained through our cycle accurate multicore NoC simulator. Using a dynamic scheduling load balancing technique, we achieved a maximum speedup multiplier of 35.97 on an 8 × 8 networked processor array using a NoC as the interconnect. [ABSTRACT FROM AUTHOR]