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3-Allyl-4-hydroxy-coumarins and pyrones were regioselectively cyclized with N-bromosuccinimide (NBS) on solid phase under microwave irradiation in excellent yield. NBS on montmorillonite K-10 clay under microwave irradiation for expeditious solvent-free regioselective cyclization has been used for the first time. [ABSTRACT FROM AUTHOR]

Synthesis of a number of hitherto unreported 4-aryloxymethylene-7-methyl-2,3-dihydropyrano[3,2-c]pyridine-5-ones 4a–h have been achieved in moderate yields by the thermal [3,3]sigmatropic rearrangement of 4-(4'-aryloxybut-2'-ynyloxy)-6-methyl-2-pyridone. [ABSTRACT FROM AUTHOR]

Oscillation-based test algorithm has been proposed and verified experimentally as an alternative to the specification--based test of analog circuits. Active filters are transformed to oscillators using nonlinear feedback, realized with a Schmitt trigger. Faults are detected based on the deviation of the oscillation frequency outside the tolerance band due to the variation of different circuit components under test. This proposed technique ensures high test precision due to the processing of the oscillation frequency with the help of a purely digital circuit. Undetectable ranges of parametric faults of circuit components have been identified by simulation with Cadence virtuoso using the 0.18 µm CMOS technology. Then, practical circuits of second order Butterworth Low Pass Filter and Sallen-Key Band Pass Filter have been tested experimentally. Experimental results ensure high fault coverage of the proposed test strategy. [ABSTRACT FROM AUTHOR]

In this paper, we present a systematic method for designing single error correcting (SEC) and double error detecting finite field (Galois field) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions to detect and correct errors. Specifically, a structural approach is first presented. The predicted parity bits are derived from the primitive polynomials for generating the fields. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesised, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Although the article considers only a finite field multiplier, without loss of generality, the technique could be applied to any combinational logic circuit. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%. Moreover, the multiple bit error detection and correction using multiple Hamming code were also introduced. [ABSTRACT FROM AUTHOR]