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This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (fLO), forming two high-impedance paths to prevent the PMOS and NMOS –gm differential pairs from loading the main LC resonator when the transistors are driven into the triode region. This improves the voltage and current efficiency of the oscillator. Furthermore, the gate-to-source voltages of the two –gm differential pairs are reshaped to reduce their phase noise contributions. Simulated in 65 nm CMOS, the proposed oscillator with 4.64–5.64 GHz (17.68%) tunability exhibits a power consumption ranging 585.9–655.4 µW while offering a phase noise performance of −139–141.5 dBc/Hz at the 10 MHz offset. The corresponding FoM is 196.2–196.7 dBc/Hz. [ABSTRACT FROM AUTHOR]

Post-fabrication inductance variation is a big issue faced by chip designers of sensitive circuits, and on-chip tunable inductors seem to provide the solution to this problem. In addition, tunable inductors also benefit circuits that require the multi-frequency operation. This paper is on the design of a tunable inductor which utilizes the patterned ground shield (PGS) to enable fine-tuning capability. This work is unique as this is the first time that the PGS is used for this purpose, previous researches were more on the Q-factor merit provided by the inductors with PGS. In this work, inductor's and PGS parameters influencing the inductance tuning range and Q-factor performances were first determined. Subsequently, inductors with PGS made from different metals and track spacing were designed, with electronic circuitries implemented to control the grounding of each PGS metal finger. The hypothesis that the floating and grounding of each PGS metal finger can change the magnetic flux of the inductor which contributes to the inductance variation was verified using Sonnet EM. Measured results show that a 5.2% inductance tuning range and Q-factor of 5.9 were achieved at the Bluetooth frequency of 2.5 GHz for an inductor with 2.0 µm track spacing and a polysilicon PGS with finger spacing of 2.0 µm. The tunable inductor was further integrated into a power amplifier (PA) and simulation results show that it enables the PA to achieve the design specification at the frequency range of 3.3–3.8 GHz, dedicated for the sub-6 GHz 5G application. [ABSTRACT FROM AUTHOR]

A low power consumption linear power amplifier (PA) for Internet of Things (IoT) application is presented. An analog pre-distorter (APD) is integrated to the PA, which consists of an active inductor, driver amplifier, and an RC phase linearizer. When measured with continuous wave signal, the PA produces more than 12 dB power gain from 2.4 to 2.5 GHz. At the centre frequency of 2.45 GHz, the PA's gain is 12.5 dB with peak power added efficiency (PAE) of 25.6% and maximum output power of 13.7 dBm. The OIP3 achieved is 29.2 dBm with supply voltage headroom of 1.8 V. The proposed APD befit to be a solution to reduce the trade-off between maximum linear output power and PAE. [ABSTRACT FROM AUTHOR]

This paper describes a 3.5-GHz up-conversion mixer core utilized in a two-step transmitter architecture in compliance with IEEE 802.11a WLAN application. The architecture is based on current-draining folded architecture and is implemented in 0.18-μm CMOS technology, which alleviates the need of bulky resonator integration. The main advantages of the introduced mixer topology are high linearity and high isolation. The low-voltage architecture consumes 5.17 mA of current from 1.8-V supply and shows –2.09-dBm IIP3 and –9.82-dBm IP1dB. The proposed architecture observes an output power of –43.69 dBm at the up-converted 3.7 GHz sideband, with –30 dBm and –10 dBm of input baseband and local oscillator power, respectively. [ABSTRACT FROM AUTHOR]

A low-voltage, low-power current-mode bandgap reference is designed and simulated in standard 0.13 μm CMOS technology on the Spectre platform. The proposed current-mode bandgap reference has a simulated temperature coefficient of 47.15 ppm/°C over the temperature range of -40°C to 140°C, with the corresponding current consumption of 42.06 μA complying with the specified temperature range. It could be operated down to 1.0 V of supply voltage headroom, while consuming 300 μW of power. [ABSTRACT FROM AUTHOR]

A low-power, low-phase noise, high tuning range, and fully integrated inductorless RC-VCO (voltage-controlled oscillator) for OC-48 application is designed and simulated in standard 0.18 μm CMOS technology. The proposed inductorless RC-VCO has a simulated phase noise of -141 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz, with a bias current of 605 μA and voltage headroom of 1.8 V. It has 50% tuning range at 2.4 GHz of operating frequency and consumes 1.09 mW of power. This RC-VCO shows a figure of merit performance of -208.2 dBc/Hz at the desired frequency. [ABSTRACT FROM AUTHOR]

This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage-controlled oscillator (QVCO), realized with pMOS transistors, relaxing the sensitivity to substrate-induced noise and flicker noise, 1 f effect. A stacked planar spiral inductor exhibiting a Q factor of 5.8, with a pMOS-based varactor of 32% tuning range is iμpleμented in 0.18 μμ CMOS technology. The phase noise of the SIPC QVCO architecture siμulated at 1 MHz of offset frequency is observed to be -111.43 dBc/Hz, in coμparison with the phase noise of a conventional QVCO architecture which is observed to be -106.15 dBc/Hz, while dissipating the saμe aμount of power about 14.6 μW. The effect of coupling factor, K to the aμplitude and phase noise degradation is also investigated and verified. [ABSTRACT FROM AUTHOR]

This paper presents a highly tunable low-resistance (high QC), low-cost Metal Oxide Semiconductor (MOS) varactor realized in the 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology for Wireless Local Area Network (LAN) high-frequency application. The varactor implemented in an accumulation-MOS mode of configuration exhibits a superior tuning percentage of 41% (0.98 pF ∼ 0.40 pF). Various MOS varactor configurations are demonstrated comparatively. [ABSTRACT FROM AUTHOR]