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Dichlorosilane (SiH2Cl2) is essential for the Selective Epitaxial Growth of Si and SiGe in the windows of patterned wafers. However, it is plagued by relatively slow growth rates at low temperatures. Meanwhile, hydrogenated silicon precursors (such as silane (SiH4), disilane (Si2H6) or trisilane (Si3H8)), yield significantly higher Si and SiGe Growth Rates (GR) at low temperatures. Such precursors are intrinsically non selective versus dielectric masking materials, but this difficulty can be overcome with advanced (Cyclic) Deposition / Etch processes. Liquid Si precursors such as trisilane have however several drawbacks: (i) they are expensive to produce with electronic-grade quality; (ii) being liquid, they require dedicated bubblers to be delivered into the growth chamber. Taking full advantage of their decomposition at very low temperatures is also not always possible, as the resulting films might be of lesser crystalline and electronic quality (gas phase nucleation and/or an adatom surface mobility which is too low). By contrast, disilane is gaseous and gives higher GR than silane (the Si-Si bond strength, 33 kcal mol.-1, is indeed weaker that the Si-H bond strength, 47 kcal. mol.-1). With the proper process parameters, it is possible to have reasonable growth rates down to 450°C only for SiGe(:B). It is thus a good choice of silicon precursor for the low temperature growth of Si and SiGe layers. This is illustrated in the following, where we have benchmarked SiH4 and Si2H6 against SiH2Cl2 for the low temperature growth of Si and SiGe in 300mm industrial Reduced Pressure – Chemical Vapour Deposition (RP-CVD) chambers from major Suppliers A and B. Si growth rates are, for T < 575°C, approximately ten times higher with Si2H6 than with SiH4, which are in turn roughly ten times higher than with SiH2Cl2 (see Figure 1). Activation energies, 49-52 kcal. mol.-1 (SiH4), 51-56 kcal. mol.-1 (Si2H6) or 60-61 kcal. mol.-1 (SiH2Cl2), are in-between the Si-H and Si-Cl bond strengths. For given GeH4 and Si precursor mass-flow ratios, lower Ge contents and significantly higher SiGe growth rates are obtained at 550°C, 20 Torr with Si2H6 than with SiH4 and especially SiH2Cl2 (see Figure 2). The dependency of the Ge content x on the F(GeH4) / F(Si precursor), linear for a SiH4 - based chemistry (x / (1-x) = 2.27–2.50 * F(GeH4) / F(SiH4)), is parabolic for Si2H6 and SiH2Cl2 based chemistries (x 2 / (1-x) = 0.51–0.58 * F(GeH4) / 2*F(Si2H6) and x 2 / (1-x) = 2.22-2.37 * F(GeH4) / F(SiH2Cl2), respectively). The associated SiGe GR increase linearly with the GeH4 mass-flow irrespective of the Si precursor used. With SiH4 and SiH2Cl2, growth rates (Ge concentrations) are typically lower (slightly lower) in Supplier A than in Supplier B chamber. The situation is the opposite with Si2H6. Growth rates (and Ge contents) are then higher in the former reactor than in the latter. This is assigned to (i) a ~ 5°C offset between the two and (ii) effective precursor flows which are different (likely due to chamber geometry differences). Growth rate activation energies and relationships linking Ge concentration to precursor mass-flow ratios are nevertheless similar, as shown in Figure 3 for the SiH2Cl2 + GeH4 chemistry and various temperatures. Process transfer between the two should be rather easy, We have otherwise assessed the interest of having an in-situ surface preparation chamber connected to the N2-purged transfer chamber of our cluster tool on interfacial contamination and epitaxial quality. There are indeed two ways of removing native oxide on a Si wafer: (i) thanks to an ex-situ “HF-last” wet cleaning followed by a short queue time loading in the N2-purged load-locks or (ii) thanks to an in-situ exposure of the wafer surface to a remote NH3/NF3 plasma which transforms native oxide into a salt which is sublimated at low temperature. As the oxide-free surface is exposed for minutes up to tens of minutes to the air in the former case, while it stays under N2 in the latter case, we would expect the second to be better. We have therefore compared both processes for Si surface preparation prior to epitaxy. Surfaces are with the in-situ process always under high purity N2. This results in a threshold H2 bake temperature (above which there is no O interfacial contamination anymore) which is shifted downwards by ~ 25°C (from 775°C down to 750°C). Below that temperature, O sheet concentrations are with the in-situ process typically one third those associated with “HF-Last” wet cleanings and epitaxial surfaces are smoother, as shown in Figure 4. Figure 1

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (