64 results on '"Endoh, T."'
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2. First-Principles Study on Shape Degradation during Oxidation Process for Three-Dimensional Structure Devices
3. Ultralow-Power and Compact Nonvolatile Brain-Inspired VLSIs Based on CMOS/MTJ Hybrid Technology
4. Cross Point Type 1T-1MTJ STT-MRAM Cell with 60 nm Multi-pillar Vertical Body Channel MOSFET under 55 nm p-MTJ and Its Beyond for High Density STT-MRAM
5. Guiding principles for the fabrication of V-MOSFETs based on a Si emission model
6. Sub 1 V 60 nm Vertical Body Channel MOSFET Based 6T SRAM Array with Wide Noise Margin and Excellent Power Delay Product
7. Highly Efficient and Compact CMOS DC-DC Converter with Novel Transistor Layout of 60 nm Multi-pillar Type Vertical Body Channel MOSFET
8. A Study of Validation of an Evaluation Model of Accurate Thermal Stability Factor for MTJs Using Its Thermal Dependency
9. Novel Integrated Voltage Regulators with High-Side NMOS Power Switch and Dedicated Bootstrap Driver Using Vertical MOSFET for Efficiency Enhancement
10. New Model of Switching Delay Induced by Modulation Effect of Damping and STT Pumping Balance with Programing Current and Interference Phenomena in p-MTJ Array
11. Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme
12. Study about the Ion Beam Etching (IBE) Process for the High Density Spintronic Devices and its Damage Recovery by the Oxygen Showering Post-treatment (OSP)
13. A Compact and Ultra-Low-Power STT-MRAM-Based Associative Memory for Nearest Neighbor Search with Full Adaptivity of Template Data Format Employing Current-Mode Similarity Evaluation and Time-Domain Minimum Searching
14. Optimization of CoFeB Capping Layer Thickness for Characterization of Leakage Spot in MgO Tunneling Barrier of Magnetic Tunnel Junction
15. A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme
16. 10 nm p-MTJ Array Design for Suppressing Switching Delay Induced by Interference Due to Magnetic Dipole Interaction for High Density STT-MRAM
17. Universal Damage Recovery Scheme using the Oxygen Showering Post-treatment (OSP) Process for Sub-20nm High Density STT-MRAM Devices
18. First-Principles Study on Hydrogen Annealing Effect in Si/SiO2 Interface by Thermal Oxidation
19. Novel Design of Electrostatic Lens Potential for Improving Bending Curvature and Transmission Probability of Drive Current for Vertical Body Channel MOSFET
20. Study about the Process Damage Mechanism of the Patterned Interface Perpendicular Magnetic Tunnel Juncotions (MTJs) by Hydrogen Ion Treatments
21. Properties of Perpendicular-Anisotropy Magnetic Tunnel Junctions Fabricated over The Cu Via
22. A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation
23. Impact of Sub-Volume Excitation for Improving Overdrive Delay Product in Sub-40nm p-MTJ and Its Beyond
24. Ultra Low-Frequency Noise in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process
25. A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit
26. A High-frequency Level-up Shifter Based on 0.18μm Vertical MOSFETs with More than 70% Reduction of Overshoot-voltage Above VDD
27. LLG Micromagnetic Simulation on STT Efficiency of sub 30nm Perpendicular MTJs with etching damage
28. Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications
29. Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell
30. A 4x4 Nonvolatile Multiplier Using Novel MTJ-CMOS Hybrid Latch and Flip-Flop
31. Strategy of STT-MRAM Cell Design and Its Power Gating Technique for Low-Voltage and Low-Power Cache Memories
32. Studies on Selective Devices for Spin-Transfer-Torque Magnetic Tunnel Junctions
33. Multi-electron Wave Packet Transport Dynamics in Nanoscale Channel
34. Size Dependence of Electrostatic Lens Effect in Vertical Pillar Type MOSFET
35. Excellent Scalability Including Self-Heating Phenomena of Vertical-Channel Field-Effect-Diode (FED) Type Capacitorless One Transistor DRAM Cell
36. Dynamical Coulomb Blockade in Multi-Electron Wave Packet Dynamics in Nanostructures
37. Properties of perpendicular-anisotropy magnetic tunnel junctions prepared by different MTJ etching process
38. Effect with Nano Dot Type Storage Layer Structure on Channel Region in 20nm Planar NAND Flash Memory Cell
39. Layout Design Considering Electro-thermal Properties for CMOS Inverter Composed of Multi-pillar Vertical MOSFET
40. A DRAM Sense Amplifier Circuit by Multi-pillar Vertical MOSFET Realizing Sub-1V Core Voltage Operation without Overdrive Technique
41. Novel Field Effect Diode type Vertical Capacitorless 1T-DRAM Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics
42. A 3-mW/Gbps 1.8-V Current-reuse LVDS Driver with 30% Power Reduction using Vertical MOSFETs
43. Effect of Coulomb Interaction in Electron Wave Packet Dynamics in Nanoscale Devices
44. Role of Synthetic Ferrimagnets in MTJs from Wave Packet Dynamics
45. A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure
46. Time-Resolved Switching Characteristic in Magnetic Tunnel Junction with Spin Transfer Torque Write Scheme
47. Nonvolatile Low Power 16-bit/32-bit MTJ Based Binary Counter and its Scaling
48. High-Speed-Search Nonvolatile TCAM Using MTJ Devices
49. A Wide-Range Tunable Level-Keeper using Vertical MOSFETs for Current-Reuse Systems
50. Disturb-free 3D vertical FG NAND with Separated-Sidewall Control Gate
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