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Submitted by Kamila Costa (kamilavasconceloscosta@gmail.com) on 2015-06-18T18:45:56Z No. of bitstreams: 1 Tese-Rodrigo Ribeiro de Oliveira.pdf: 2799682 bytes, checksum: 60b9680a231c5e27560663458d4e673d (MD5) Approved for entry into archive by Divis??o de Documenta????o/BC Biblioteca Central (ddbc@ufam.edu.br) on 2015-06-19T20:40:50Z (GMT) No. of bitstreams: 1 Tese-Rodrigo Ribeiro de Oliveira.pdf: 2799682 bytes, checksum: 60b9680a231c5e27560663458d4e673d (MD5) Made available in DSpace on 2015-06-19T20:40:50Z (GMT). No. of bitstreams: 1 Tese-Rodrigo Ribeiro de Oliveira.pdf: 2799682 bytes, checksum: 60b9680a231c5e27560663458d4e673d (MD5) Previous issue date: 2015-03-27 This PhD thesis presents a novel hardware reconfiguration methodology, which uses the digital TV broadcast signal for reconfiguring hardware modules in digital TV receivers. The proposed methodology allows hardware cores to be signaled, during the transport stream generation step, transmitted and then reassembled. At the receiver, the recovered cores are then used to reconfigure reprogrammable field programmable gate array (FPGA) devices, which are integrated into each receiver unit. Besides, content signaling allows receivers to choose between FPGA cores synthesized for different manufacturers, which enables receivers to select broadcast hardware cores related to the employed FPGA models. The results of the performed experiments, which were carried out during the development of this work, consist in a proof of concept and show the technical feasibility of this methodology, regarding reconfiguration of pre-synthesized hardware cores through the digital TV environment. Receiver manufacturers could benefit from this methodology for developing reconfigurable architectures, which would allow the incorporation of technological advances into receiver hardware and provide better control regarding product life cycle. As a result, future revisions of DTV standards could occur without the need for device replacement. Esta tese de doutorado apresenta uma metodologia de reconfigura????o de hardware, que utiliza o sinal da emissora de TV digital como base para atualizar m??dulos de receptores de TV digital. A metodologia proposta permite que n??cleos de hardware sejam sinalizados, durante a gera????o do fluxo de transporte, transmitidos e posteriormente remontados. Desse modo, os n??cleos recebidos s??o usados na reconfigura????o de dispositivos baseados em l??gica reprogram??vel (field programable gate array - FPGA), que est??o integrados ao hardware de cada unidade receptora. Al??m disso, a sinaliza????o de conte??do permite a distin????o entre n??cleos sintetizados para FPGAs de diferentes fabricantes, o que habilita receptores de TV digital a selecionar somente n??cleos de hardware relativos aos modelos de FPGA utilizados. Os resultados obtidos com os experimentos realizados, durante o desenvolvimento deste trabalho, consistem em uma prova de conceito e demonstram a viabilidade t??cnica do uso desta metodologia de transmiss??o e reconfigura????o, para n??cleos pr??-sintetizados de hardware enviados em um ambiente de televis??o digital. Fabricantes de receptores poderiam utilizar os benef??cios desta metodologia para o desenvolvimento de arquiteturas reconfigur??veis, o que permitiria a incorpora????o de avan??os tecnol??gicos ??s fun????es de hardware do receptor e um maior controle do ciclo de vida de produto. Como resultado, futuras revis??es de normas de TV Digital n??o resultariam em troca de equipamento.