Search

The proliferation of artificial intelligence (AI) has opened up new avenues for the modeling of power electronics with ultra-fast transient responses, such as wide-bandgap (WBG) devices. This paper highlights the significance of ultrafast transient device-level hardware emulation for the DC railway microgrid (DRM) in real-time. To this end, the proposed approach partitions the DRM power system by transmission line method (TLM) and employs gated recurrent unit (GRU) and electromagnetic transient (EMT) modeling techniques for system-level subsystems. Meanwhile, for WBG devices, gallium nitride (GaN) high electron mobility transistors (HEMT) and silicon carbide (SiC) insulated gate bipolar transistors (IGBT) are modeled using a novel physical feature neuron network (PFNN), which offers high flexibility with a variable time-step (as low as 1ns), thereby improving the accuracy, efficiency and accelerating the emulation on the field-programmable gate array (FPGA). The effectiveness of the proposed approach is confirmed by comparing the emulation results with offline simulation results obtained from PSCAD/EMTD for system-level and SaberRD for device-level transients. The proposed PFNN approach provides strong versatility, ultra-fast transient emulation capability, and significantly improved accuracy, which bodes well for the future of power electronics device-level emulation.

Maritime industries desire high speed and reliability, low lifespan cost, and environmental impact shipping for transportation. Compared to highly congested land shipments and high-cost air freight, all-electric ship (AES) can reduce the lifespan energy consumption and transport a considerable freight volume at a lower rate. Recently, the medium voltage DC (MVDC) topology, recommended by IEEE standard, pushes the AES to the next stage in considering space and weight constraints with the reduction of bulky transformers and simplified parallel connections. However, device-level modeling of this massive parallel MVDC-based ship-board microgrid (SBM) is challenging to both the state-of-the-art general-purpose compute unit and traditional electromagnetic transient (EMT) based emulation. With the rapid development of machine learning (ML) algorithm and its dedicated execution unit, accelerated parallel emulation becomes achievable in different levels of this paralleled connected SBM. Applying the ML-aided technique can help to improve the emulation execution efficiency and reduce the consumption of hardware resource on the field-programmable gate arrays (FPGAs). This work proposes a real-time hybrid ML-EMT based digital twin of the complete SBM at the subsystem-level and equipment-level with validated results from PSCAD/EMTDC, and device-level with validated results from SaberRD.