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A method of reducing LUT count in the FPGA-based circuit of Mealy finite state machine (FSM). A part of the circuit is implemented using embedded memory block (EMB). The method is based on the twofold state assignment and encoding collections of microoperations. An example of the synthesis of FSM circuit using the proposed method is given. When certain conditions are met, there are exactly three levels of logic elements in the FSM circuit. Methods for improving the characteristics of a circuit based on optimal coding of states and collections of microoperations are considered. [ABSTRACT FROM AUTHOR]

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