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The modeling and characterization of low-frequency noise and noise variability in various regimes of operation are investigated for the main advanced complementary metal–oxide semiconductor (CMOS) technologies. Novel materials and innovative device architectures from 0.5 μm to 20 nm gate lengths are studied. The impact of gate stack, realized with ultrathin oxides, polysilicon gate and high-k/metal gate is analyzed. The influence of alternative channel materials, in particular ultrathin body silicon-on-insulator layers, strain Si and III–V materials is addressed. The comparison of low-frequency noise in advanced device architectures, including bulk Si, fully depleted SOI, FinFET, junctionless, and multi-gates structures, is shown. Accurate noise models, taking into account the main physical mechanisms, are proposed for all these very advanced technologies, which will be needed for the nanoelectronics of the next decade. Copyright © 2015 John Wiley & Sons, Ltd.

An analytical expression for the three-dimensional potential distribution along the channel of short channel silicon multi-gate MOSFETs is described in weak inversion. The analytical solutions cover three different cases of multi-gate devices: Symmetrical double gate (DG), tri-gate (TG) and gate-all-around (GAA) MOSFETs. Using the three-dimensional potential distribution in the silicon film, the subthreshold drain current is calculated from which the threshold voltage and the subthreshold swing were extracted. The threshold voltage roll-off, the subthreshold swing and the drain-induced barrier lowering of the multi-gate devices are compared, showing the critical advantage of GAA structures concerning the short channel effects. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this paper a comparison in the performance of two analog buffers for Active Matrix Displays (AMDs) applications is presented. The two buffers are implemented by using low-temperature polysilicon thin-film transistors (LT poly-Si TFTs) presenting high immunity to the threshold voltage variations of the TFTs devices. The verification of their functionality and performance was made through simulation with Synopsys HSpice. In order the simulations to be realistic and the performance as close to reality as possible, parameters extraction was made from fabricated LT poly-Si TFTs. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The low frequency (LF) noise and random telegraph signal (RTS) fluctuations in 0.189 μm complementary metal-oxide-semiconductor (CMOS) devices are investigated. We find that the 1/f noise stems from fluctuations in the carrier number of both N and P channel MOS devices. The slow oxide trap concentration deduced from the noise data is 10 17 /ev cm 3 in agreement with previous 0.35 to 0.25 μim technologies and state-of-the-art gate oxides. The study of some particular RTSs is performed and provides the gate voltage dependence of the capture/emission times as well as of the drain current RTS amplitude. Drain current RTS amplitudes as large as 5 to 10%, have been observed, being somewhat larger than for 0.35 to 0.25 μm CMOS technologies. In addition, the dispersion of the noise level measured at a fixed biasing current and frequency is investigated as a function of the device gate area, showing a considerable large sample-to-sample variation for the smallest devices. Finally, the residual noise backgrounding the RTS noise is studied as a function of gale voltage for some RTSs and is found to be a white noise presumably associated to RTSs with higher cut-off frequencies.

A surface roughness mobility model for silicon MOS transistors is proposed. This mobility model, which predicts an exponential decrease of the mobility with the normal electric field and with the surface micro-roughness at the Si-SiO2 interface, provides a simple physical insight into the mobility attenuation at high electric fields. The model is successfully validated by comparison to mobility data obtained at high gate voltages and/or low temperature. Moreover, its capability to fit the mobility reduction with the interface micro-roughness reported by Ohmi et al. is also demonstrated and strongly supports its physical basis.

The carrier mobility in N- und P-channel MOSFET's at high transverse electric field is studied from room to liquid helium temperature. It is shown that the negative transconductance phenomenon obtained at high gate voltage is enlarged by decreasing the temperature. This behavior is attributed to a change in the mobility law for high transverse electric field. An accurate extraction method is proposed in order to determine the new parameters involved in the mobility and the drain current laws. These new relations are successfully employed for the fitting of experimental results obtained with MOS devices from various technologies.

DC characterization of n MOS inverters is carried out from liquid helium up to room temperatures. The benefits resulting from the low temperature operation on the performances of the n MOS inverter are studied. In particular, the improvement of the switching gain at low temperature is pointed out. Moreover, the relative noise margin is found to increase significantly at low temperature (≈50K). The possibility to operate the n MOS inverter at low temperature while reducing the supply voltage and in turn the power consumption is emphasized.

The wearout and breakdown parameters of representative gate and tunnel oxides are evaluated versus temperature, electric field and polarity. A frontier close to 127°C between two regions with different activation energies is clearly demonstrated. However, the negative charge build-up under high field stress is correlated with the breakdown. The field acceleration factor is found to be constant in the range 8·5–12·5 MV/cm. The time-to-breakdown distributions can be described both by the E and the 1/E models. Finally, the thickness dependence of the field acceleration factor is quantified for oxide layers with a thickness in the range between 10 nm and 50 nm.

The reliability issues of offset drain transistors (ODTs) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress are attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO2 interface state charge.

A SPICE model which enables transient simulations of the programming window degradation in FLOTOX EEPROM cells to be performed is presented. The simulation enables the endurance characteristics of the memory cells to be predicted at CAD level, when provided with the memory cell geometry, the programming conditions and the tunnel oxide quality. Thereby, the optimization of the cells' geometry with respect to the endurance performance as well as the selection of the optimum programming conditions which minimize the window degradation become possible, even prior to the fabrication of the memory cells.

A theoretical analysis of the impact of scaling down on the low frequency noise characteristics of silicon MOS transistors is presented. This analysis is based on the assumption that low frequency noise in large area MOS devices arises from the superposition of many RTS (random telegraph signal) fluctuators. An analytical formula for the input gate voltage noise in large area devices is derived from the RTS approach, reconciling the McWhorter and the RTS approaches. Moreover, we show that, for a realistic scaling law, the miniaturization of the devices will lead to an increase of the mean noise level linearly with the scaling factor and to a substantial (≈three orders wide) sample-to-sample noise level dispersion, whereas for a classical scaling law, the mean noise is found to be independent of scaling. Finally, it is shown that the miniaturization will also result in a strong evolution of the noise spectra from 1/f to Lorentzian like for devices with channel lengths from 1 to 0.1 Nm. Eine theoretische Analyse des Einflusses der Impulsuntersetzung auf die Niederfrequenzrauschcharakteristik von Si-MOS-Transistoren wird dargestellt. Die Analyse basiert auf der Annahme, das niederfrequentes Rauschen in grosflachigen MOS-Bauelementen aus der Uberlagerung vieler RTS-Fluktuationen herruhrt. Aus der RTS-Naherung wird eine Formel fur das Eingangsgatespannungsrauschen in grosflachigen Bauelementen hergeleitet, die die Naherungen von McWorther und RTS in Einklang bringt. Weiterhin wird gezeigt, das fur ein realistisches Untersetzungsgesetz die Miniaturisierung der Bauelemente das mittlere Rauschniveau linear mit dem Untersetzungsfaktor vergrosert und zu einer erheblichen Rauschniveaudispersion fuhrt, wahrend fur den klassischen Fall das Rauschniveau unabhangig vom Untersetzungsfaktor ist. Schlieslich fuhrt eine Miniaturisierung zu einer starken Verschiebung des Rauschspektrums von einer 1/f- zu einer Lorentz-Funktion hin fur Bauelemente mit Kanallangen zwischen 1 und 0,1 μm.

A theoretical analysis for the calculation of the conductance fluctuations in small area metal–oxide–semiconductor (MOS) devices is presented. This analysis relies essentially on the assumption that the trap region in the device channel can be approximated by a rectangular region inside which the sheet conductivity differs from that in the region of the channel outside the trap. The sheet conductivity shift in the trap region is evaluated using the concept of flat band voltage shift associated with the trapping of one elementary charge in the trap region. The approach of flat band voltage shift is then advantageously used to derive first-order analytic expressions of the random telegraph signal (RTS) amplitude. In particular, it is found both, analytically and numerically that, in the case of small sheet conductivity modulation, the RTS amplitude becomes independent of the trap size. The numerical simulations show that the maximum RTS amplitude occurring in weak inversion is not a monotonic function of the trap size. Indeed, the normalized conductance fluctuation does increase as the trap area is reduced, passes through a maximum and finally decreases towards zero. The comparison of the simulation results with typical experimental RTS data shows an overall good agreement. In particular, it is clearly demonstrated from the RTS measurements that the gate voltage dependence of the normalized RTS amplitude can be strongly correlated to that of the transconductance to drain current ratio gm/Id. Eine theoretische Analyse fur die Berechnung der Leitfahigkeitsfluktuationen in kleinflachigen Metall–Oxid–Halbleiter(MOS)-Bauelementen wird angegeben. Diese Analyse beruht wesentlich auf der Annahme, das der Haftstellenbereich im Bauelementekanal durch einen rechteckigen Bereich genahert werden kann, indem die Schichtleitfahigkeit sich von der im Kanalbereich auserhalb der Haftstelle unterscheidet. Die Schichtleitfahigkeit im Haftstellenbereich wird mit dem Konzept der Flachbandspannungsverschiebung, die mit dem Anhaften einer elementaren Ladung im Haftstellenbereich verbunden ist, berechnet. Dieses Verfahren der Flachbandspannungsverschiebung wird dann vorteilhaft benutzt, um analytische Ausdrucke erster Ordnung fur die Amplitude des statistischen Telegraphensignals (RTS) abzuleiten. Insbesondere wird sowohl analytisch als auch numerisch gefunden, das im Falle einer geringen Schichtleitfahigkeitsmodulation die RTS-Amplitude unabhangig von der Haftstellengrose wird. Die numerischen Simulationen zeigen, das die maximale RTS-Amplitude, die in schwacher Inversion auftritt, keine monotone Funktion der Haftstellengrose ist. Tatsachlich nimmt die normierte Leitfahigkeitsfluktuation zu, wenn die Haftstellenflache verringert wird, geht durch ein Maximum und nimmt endlich auf null ab. Der Vergleich der Simulationsergebnisse mit typischen experimentellen RTS-Daten zeigt eine gute Gesamtubereinstimmung. Insbesondere wird aus den RTS-Messungen klar gezeigt, das die Gatespannungsabhangigkeit der normierten RTS-Amplitude streng mit der des Steilheits–Drainstromverhaltnisses gm/Id korreliert werden kann.

MOS transistors with very thin oxide (8.5 nm) are concurrently investigated using static I(U), charge pumping, and low frequency noise measurements before and after Fowler-Nordheim injections. The reliability of the structures is assessed by means of fixed oxide charge, and fast and slow interface trap density variations as a function of stress. The noise characteristics of the devices before and after stress are found to be attributable to carrier number fluctuations. Moreover, it is found that the slow interface trap densities deduced from noise measurements are well correlated to the fast interface state ones measured both, by the subthreshold slope and the charge pumping techniques. This proves the ability of noise measurements to be a useful complementary tool for the characterization of the electrical properties of the silicon- oxide interface. MOS-Transistoren mit sehr diinnem Oxid (8,5 nm) werden gleichzeitig mittels statischer I(U)-Charakteristiken, Ladungspumpen und Niederfrequenz-Rauschmessungen vor und nach Fowler-Nordheim-lnjektion untersucht, Die Zuverlassigkeit der Strukturen wird mittels fester Oxidladungen und schnellen sowie langsamen Grenzflachenhaftstellenanderungen in Abhangigkeit von der Spannung beurteilt. Die Rauschcharakteristiken der Bauelemente vor und nach Spannungseinflus konnen der Tragerzahlfluktuation zugeordnet werden. Daruber hinaus wird gefunden, das die Dichten der langsamen Grenzflachcn haftstellen, die- aus den Rauschmessungen abgeleitct werden, gut mit den schneilen Grenzflachenzustanden korrelieren, die sowohl mit dem Subschwellenanstieg als auch mit der Ladungspumptechnik gemessen werden. Dies bestatigt, das die Rauschmessungen eine nutzliche komplementare Methode zur Charakterisierung der elektrischen Eigenschaften der Silizium Oxid-Grenzflache darstellen.

An improved analysis of low frequency trapping noise in a MOS device is proposed. This analysis takes into account the supplementary fluctuations of the mobility induced by those of the interface charge. It enables an adequate description of the gate voltage dependence of the input equivalent gate voltage noise to be obtained in various actual situations. The outputs given by the Hooge mobility fluctuation model are also presented and discussed with respect to those obtained by the carrier number fluctuation model. In particular, the impact of the channel length or channel width, and the model type on the input gate voltage and drain current noise characteristics is studied and compared to typical experimental data. Finally, a procedure for the diagnosis of the low frequency noise sources in a MOS transistor is proposed.

A numerical model for the ohmic operation of depletion-mode MOS transistors operated at very low temperature is presented. This model which is based on a quantum treatment of the accumulation layer and on a specific mobility law enables a good modelling of the transfer characteristics Id(Ug) and gm(Ug) to be obtained from weak to strong accumulation. An analytical version of this model is also derived for the strong accumulation region above flat-band. This model relies on simple analytical expressions which contain only three parameters i.e. the flat-band voltage Vfb, the maximum mobility μm and the mobility attenuation factor θlt. Moreover, a method for the extraction of the depletion-mode MOSFET parameters based on the plot of the I/g(Ug) characteristics is presented. Ein numerisches Modell fur den ohmschen Bereich von MOS-Verarmungstransistoren bei sehr tiefen Temperaturen wird angegeben. Dieses Modell, das auf einer Quantenberechnung der Akkumulationsschicht und einem spezifischen Beweglichkeitsgesetz beruht, erlaubt eine gute Modellierung der Transfercharakteristiken Id(Ug) und gm(Ug) im Bereich zwischen schwacher und starker Akkumulation. Eine analytische Version dieses Modells wird auch fur den starken Akkumulationsbereich oberhalb Flachband abgeleitet. Dieses Modell beruht auf einfachen analytischen Ausdrucken, die nur drei Parameter, die Flachbandspannung Ufb, die Maximalbeweglichkeit μm und den Beweglichkeitsdampfungsfaktor θlt enthalten. Daruberhinaus wird eine Methode zur Bestimmung der MOSFET-Verarmungsparameter angegeben, die auf der Auftragung von I/g (Ug)-Charakteristiken beruht.

A study is made of the effect of thermal annealing on defect annihilation in arsenic implanted silicon. The combination of electrical measurements and transmission electronic microscopy analysis allows us to demonstrate the existence of a low energy thermally activated process. This process occurs in the highly damaged surface layer induced by the arsenic implantation and is efficient well below the solid phase epitaxy transition temperature. It is suggested that point defect migration should play an important role in the electrical impurity activation at low annealing temperatures. Nous avons etudie l'effect du recuit thermique sur les mecanismes de restructuration des couches de silicium fortement endommagees par implantation ionique. La combinaison des mesures electriques et de l'analyse par microscopie electronique sur section nous a permis de dissocier la recristallisation des couches amorphes, produites par l'implantation de l'arsenic a tres fortes doses, d'un autre phenomene d'activation electrique caracterise par une faible energie d'activation et se deroulant a des temperatures de recuit inferieures a celles caracteristiques de la croissance par epitaxie en phase solide.

The degradation is investigated of submicron MOS transistors after electrical stress. New methods for the aging investigation based on field effect mobility measurements are presented. The correlations between the different degradation parameters are studied and analysed by a one-dimensional modelling that takes into account the potential fluctuations induced by the surface state and charge generation. Moreover, the degradations are found to increase with the bias parameter K = Ug/Ud applied during stress. In addition, the partial reversibility of degradations shows that electron trapping appears as the main cause of aging. Ce papier s'interesse a la degradation des transistors MOS apres contrainte electrique. De nouvelles methodes d'investigation du vieillissement basees sur des mesures de mobilite d'effet de champ sont presentees. Les correlations entre les differents parametres de degradation sont etudiees et analysees par un modele uni-dimensionnel qui prend en compte les fluctuations de potentiel induites par la creation d'etats et de charges de surface. De plus, on trouve que les degradations augmentent comme le parametre de contrainte K = Ug/Ud. Enfin, la reversibilite partielle des degradations montre que le piegeage d'electrons apparait comme la cause principale des vicillissements observes.

A theoretial analysis of the surface charge noise at the Si-SiO2 interface is presented. The interface state charge spectral density is evaluated as a function of the interface state conductance associated with the energy dissipation due to the electronic exchanges into the interface state reservoir. The interface charge noise spectrum is investigated using different electrical models of the Si-SiO2 interface. Moreover, a compact formulation of the drain current spectral density both for enhanced and depletion mode MOSFETs is established. It allows a complete analysis of the frequency, gate bias, and temperature dependence of the noise spectrum characteristics of an MOS transistor. Une analyse theorique du bruit de la charge de surface a l'interface Si-SiO2 est, presentee. La densite spectrale de la charge d'interface est evaluee en fonction de la conductance des etats d'interface associee a la dissipation d'energie dans le reservoir des etats d'interface. Le spectre de bruit de la charge d'interface est investigue en utilisant differents modeles electriques de l'interface Si-SiO2. De plus, une formulation compacte de la donsite spectrale de courant pour des MOSFETs a enrichissement et a depletion est etablie. Elle permet une analyse complete de la dependance en frequence, en tension de grille et en temperature des caracteristiques spectrales de bruit d'un transistor MOS.

An analytical model of conductance and transconductance for depletion-mode MOS transistors is presented. Based on a proper charge and mobility analysis, the model enables the calculation of the conductance and transconductance characteristics against several technological parameters such as substrate doping, oxide thickness or interface state density. It is shown how the field effect mobility variations with gate voltage differ from those of enhanced-mode MOSFETs. It is also emphasized that this model provides a useful tool for the characterization of depletion-mode MOS devices.

An analytical model of conductance and transconductance for enhanced-mode MOSFETs is presented. Based on an inversion charge dependent mobility, the model enables the calculation of the conductance and transconductance MOSFET characteristics against several parameters such as bulk bias, oxide thickness, channel length, source-drain series resistance, surface states density, mobility reduction factor and/or potential fluctuation rate. The maximum field effect mobility and the extrapolated threshold voltage deduced from transfer characteristics are then investigated as a function of these parameters. It is finally emphasized that this MOSFET modelprovides a simple but useful tool for analysing the limitations of scaled down devices. Un modele analytique de conductance et de transconductance pour MOSFET a enrichissement est presente. Ce modele base sur une dependance de la mobilite avec la charge d'inversion permet de calculer la conductance et la transconductance de MOSFETs en fonction des parametres tels que la polarisation du substrat, L'epaisseur de L'oxide de grille, la longueur du canal,la resistance serie source-drain, la densite d'etats d'interface, le facteur de reduction de la mobilite et/ou le taux de fluctuation de potentiel. Le maximum de la mobilite d'effet de champ et la tension de seuil extrapolee deduites des caracteristiques de transfert sont analysees en fonction de ces parametres. II est finalement souligneque ce modele de MOSFET procure un outil simple mais utile pour L'investigation des limitations propres a la miniaturisation des dispositifs.