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This paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits. [ABSTRACT FROM AUTHOR]

This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network. Due to the non‐linear function fitting capability of the neural network, the linearity of the ADC is improved effectively. However, the hardware complexity of the neural network limits its application and promotion in ADC calibration. Hence, this paper also presents the optimization schemes, including the neuron‐based sharing neural network and the partially binarized with fixed neural network, in terms of calibration architecture and algorithm. A 60 MS/s 14‐bit pipelined‐SAR ADC prototyped in 28‐nm technology is utilized to verify the feasibility of the proposed calibration method. The measurement results show that the proposed calibration greatly enhances the Spurious Free Dynamic Range (SFDR) and Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) from low frequency to Nyquist frequency. Meanwhile, the original calibrator and improved calibrator are synthesized in Synopsys Design Compiler to compare their hardware complexity. Compared with the unoptimized version, the optimized schemes can decrease the logic area and the network weights up to 76% and 52%, with negligible loss in calibration performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

The time‐interleaved analog‐to‐digital converter (TIADC) system could achieve high sampling rate effectively, but the frequency response inconsistency among channels will introduce frequency response mismatches, which will seriously degrade the signal quality. In this paper, a novel multi‐channel frequency response mismatches adaptive calibration method is proposed. The frequency response of the compensation filter is expanded into a polynomial of a digital differentiator, and the least mean square adaptive strategy is used to calibrate frequency response mismatches. It does not require measuring the channel frequency responses in advance and uses digital post‐processing technology to effectively compensate the frequency response of the multi‐channel TIADC system and improve the spurious‐free dynamic range. The experimental results verify the effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

A new quick-scanning extended X-ray absorption fine-structure (QEXAFS) system for in situ studies has been developed and tested on the general XAFS beamline at the Shanghai Synchrotron Radiation Facility. In the new system, an analog-to-digital converter (ADC) with 1 MHz sampling rate is used to acquire the detector data while one scaler is used to precisely calculate the scanning energy. Two external hardware trigger signals were adopted to synchronize the data collection of the ADC and the scaler. The software development platforms of the double-crystal monochromator control system and the new QEXAFS system have been unified with the Experimental Physics and Industrial Control System. By comparing the spectra acquired by the conventional step-by-step XAFS system with an energy range of 1200 eV at the 7.5um Cu foil K-edge, the new system demonstrates satisfactory signal-to-noise ratio and energy resolution. The previous shortcomings, including distortion of the spectrum and energy shift, have been overcome. The tests with different integration times indicated that appropriate parameters not only ensure good experimental results but also enhance the smoothness of the XAFS spectrum at high energy zones. The reliability of the new system has also been verified. [ABSTRACT FROM AUTHOR]

The parallel analogue to digital converter (ADC) structure with mixers such as digital bandwidth‐interleaving ADC (DBI‐ADC) is a practical structure for realising the wideband data acquisition system. The system calibration relies on accurate system frequency response measurement. However, existing measurement methods require complex synchronous circuits or are susceptible to noise. This paper proposes a new frequency response measurement method, which can be realised by a simple circuit without any synchronisation measures. At the same time, frequency response measurement can ensure sufficient accuracy. Simulation and experiment results show that the method is effective and feasible. [ABSTRACT FROM AUTHOR]

This letter presents an accuracy enhancement technique utilized in 16 bit fully differential successive‐approximation‐register analog‐to‐digital converters (SAR ADC). For noise performance improvement to obtain a higher ENOB, the residue measurement technique which statistically estimates the input residual error of comparator with Gaussian noise fitting is presented. The ADC digital output is compensated by the residue measurement results. It is verified in the 0.18‐μm 1P5M 5 V CMOS process. Finally, a 93.1 dB SNR and a 110.5 dB SFDR are measured operating at 1 MS/s with a 10‐kHz input tone and larger than 1‐dB SNR improvement is obtained in different chips. [ABSTRACT FROM AUTHOR]

Equivalent‐time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down‐conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in‐phase/quadrature gain imbalance instead of requiring a high‐speed analog‐to‐digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent‐time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent‐time sampling using DDC. [ABSTRACT FROM AUTHOR]

This paper focuses on a multi-user full-duplex massive multiple-input multiple-output amplify-and-forward relaying system with low-resolution analogue-to-digital convertors (ADCs). By modelling the loop-interference and quantisation noise as additive noise, we perform the analyses of the achievable spectral efficiency (SE) by considering the two canonical processing schemes, maximum ratio combining/maximal ratio transmission (MRC/MRT) and zero-forcing receive/zero-forcing transmission (ZFR/ZFT), respectively. Specially, we first obtain the tractable closed-form expressions of the achievable SE. Then, we present the asymptotic analyses under three different power-scaling scenarios. Comparison analysis shows that the low-resolution quantisers impose more performance loss on ZFR/ZFT schemes than MRC/MRT ones. At the same time, it is found that with different power-scaling schemes, the systems have different capabilities to restrict the effect of loop interference and lowresolution ADCs. Specially, the impact of both the loop-interference and quantisers on achievable SE can be restricted effectively only under the power-scaling scenario where the relay's transmission power is scaled down with the number of transmit antennas and the sources' transmission power is fixed. For the power-scaling case where the transmission powers of both relay and sources are scaled down simultaneously with the number of antennas, only the effect of the loop interference can be restricted, but the one of low-resolution quantisers remains. [ABSTRACT FROM AUTHOR]

This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current. [ABSTRACT FROM AUTHOR]

Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors' modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors' system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range. [ABSTRACT FROM AUTHOR]

The associated discrete circuit (ADC) model for switches is widely used in electromagnetic transient simulation of power electronic system. When using ADC model, the problem of virtual power loss caused by L/C switching cannot be ignored and small time‐step (≤2 μs) is usually required to guarantee accuracy, both of which will limit the application of ADC model. To cope with this, a fractional time‐step simulation method (FTSSM) suitable for the ADC model of power electronic system is proposed. The method is derived from the compact form of electro‐magnetic transient program (EMTP) algorithm, and the simulation iteration is implemented by small‐step synthesis calculation with different fractional time‐steps, which are designed to locate the accurate switching actions. In this way, the simulation can be conducted under larger time‐step (to tens of μs) while the accuracy is still acceptable. Further analysis on time domain error and numerical stability of the FTSSM are discussed. Simulations of grid‐connected inverter system and permanent magnet synchronous motor (PMSM) driving system are done, using FTSSM and on PSCAD respectively for comparison. The results verify the accuracy of proposed FTSSM, and indicate that the FTSSM is helpful to accelerate the offline simulation and improve the real‐time simulation performance. [ABSTRACT FROM AUTHOR]

Computing‐in‐memory (CIM) is considered a feasible solution to the acceleration of multiply‐accumulate (MAC) operations at low power. The key to CIM is parallel MAC operations in the memory domain, and thus reductions in power consumption and memory‐access latency. Resistive random access memory (RRAM) can be a good candidate for the memory for CIM given its data nonvolatility, high data density, low‐latency read‐out, multilevel representation, and inherent current accumulation capability. Particularly, the last two attributes offer analog MAC operations in parallel in the memory domain. However, the fully analog MAC operation scheme causes significant power and area overheads for its peripheral circuits, particularly, analog‐to‐digital converters. To compensate for these downsides using digital processing, a method for sub‐array‐wise partial MAC operations over weight‐resistors that are optimally split to minimize power and area overheads for the peripheral circuits is proposed. The simulations performed highlight the optimal sub‐array of 4×w/2 in size. That is, weight‐splitting such that a single w‐bit weight is represented by w/2 RRAM cells, i.e., 2‐bit for each cell. For 8‐bit weights, the figure of merit (FOM) for this optimal case reaches ≈28.3× FOM for the case of no weight‐splitting. [ABSTRACT FROM AUTHOR]

Oscillation-based testing of analog-to-digital converters represents a viable option for low-cost built-in self-testing in mixed-signal design. While numerous papers have addressed implementation issues, little attention has been paid to the measurement accuracy. In this letter, we highlight an inherent measurement uncertainty which has to be considered when deriving the parameters from the oscillation frequency. [ABSTRACT FROM AUTHOR]

This study aimed to present a comprehensive assessment of anaplastic lymphoma kinase (ALK) rearrangements evaluated by DNA/RNA‐based next‐generation sequencing (NGS) and Ventana immunohistochemistry (IHC) in patients with non‐small‐cell lung cancer (NSCLC) and to evaluate the therapeutic outcomes of ALK tyrosine kinase inhibitor (TKI) treatment. We investigated ALK gene fusions in 14,894 patients with NSCLC using Ventana IHC and NGS, including 12,533 cases detected via DNA‐based NGS and 2,361 cases using RNA‐based NGS. The overall percentage agreement (OPA), positive percentage agreement (PPA), and negative percentage agreement (NPA) were calculated when comparing the results between NGS and IHC. The therapeutic responses to ALK‐TKIs were also evaluated. In total, 3.50% (439/12,533) of specimens were NGS ALK‐positive (NGS‐p) in the DNA‐based NGS cohort and 3.63% (455/12,533) were IHC ALK‐positive (IHC‐p). The OPA of NGS was 99.60%, whereas its PPA and NPA were 92.75 and 99.86%, respectively. In the adenocarcinoma (ADC) subcohort, the PPA was 95.69%. In the RNA‐based NGS cohort, 2.20% (52/2,361) of specimens were NGS‐p and 2.63% (62/2,361) were IHC‐p. The OPA of NGS was 99.49%; its PPA and NPA were 82.26 and 99.96%, respectively. Thirteen patients with discordant results received ALK‐TKI treatment. In the seven NGS‐p/IHC‐negative (IHC‐n) patients, the overall response rate (ORR) was 85.4% (6/7) and the disease control rate (DCR) was 100%. In the six NGS‐negative/IHC‐p patients, the ORR was 66.7% (4/6) and the DCR was 100%. In summary, a high concordance of ALK gene fusion detected via NGS and IHC was observed in this study. DNA‐based NGS had a higher OPA, PPA, and PPA in the ADC subcohort, whereas RNA‐based NGS had a higher NPA. Overall, the results suggest that the combination of NGS and IHC can improve the accuracy of ALK fusion detection; hence, a result determination algorithm for clinical detection of ALK gene fusion was also proposed. [ABSTRACT FROM AUTHOR]

This study describes two new methods of sensing the speed of a pulse-width modulation-driven brushed DC motor based on measuring the inductive spikes generated when the motor is turned off. The research has studied the relationship between the rise time or duration of the inductive spike, and the motor current and speed. Computationally inexpensive algorithms have been developed that use either rise time or duration to estimate speed. The algorithms have been implemented on an inexpensive microprocessor and show a speed error of approximately 10% over most of the motor's range of operation. The spike rise time implementation requires an analog-to-digital converter (ADC) as found in many microprocessors, while the spike duration implementation requires only a single digital input thus reducing the cost of the controlling microprocessor. This work has shown that sensorless speed measurement can be based on the inductive spike and has also raised future research questions, such as to the best way to optimise the speed measurement in dynamic situations, and measurement errors to be expected in a mass production environment. [ABSTRACT FROM AUTHOR]

Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique. [ABSTRACT FROM AUTHOR]

Static testing of analog-to-digital (A/D) and digital-to-analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built-in self-test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations. [ABSTRACT FROM AUTHOR]

The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor inaccuracy errors in a split‐CDAC. By using a digital pseudo‐random number (PN) generator and paired comparators with opposite offsets, a dither‐less background calibration quickly reaches the target signal‐to‐noise‐and‐distortion ratio (SNDR) within 5 × 104 samples for various process uncertainties. The simulated performance using a behavioural 6‐bit + 6‐bit ADC with 1‐bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration. [ABSTRACT FROM AUTHOR]

A generalised space vector pulse width modulation (SVPWM) framework for the realisation of all double switching states with a memory-optimised method is proposed to reduce the total harmonic distortion (THD) and to provide neutral point voltage balancing for three-level NPC voltage source inverter (VSI). The proposal provides an efficient SVPWM implementationwith reduced hardware requirement and zero increase in software complexity in comparison to the existing schemes. Microcontroller analogue-to-digital converter (ADC) hardware replaces multichannel ADC and associated Field programmable gate array hardware in this proposal. The proposed method follows digital control architecture and eliminates the need to sample phase voltages separately. The proposed algorithm samples rms voltage of one phase and generates eight bit modulation index command by a suitable compensation algorithm. The implemented SVPWM algorithm takes the modulation index command value and generates phase voltage values by multiplying with the stored sine angle values. Gate pulses are generated in the proposed implementation by the hardware pulse width modulation (PWM) block and there is no need for digital-to-analogue converter. The proposed strategy is validated with a fundamental frequency of 50 Hz on a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI using low-cost PIC microcontroller. The superiority of the proposed method lies in providing an efficient three-level SVPWM implementation with reduced THD, neutral point voltage balancing, reduced hardware requirement, small lookup table and zero increase in the software computing overhead. [ABSTRACT FROM AUTHOR]

The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs. [ABSTRACT FROM AUTHOR]

This study presents a direct power control (DPC) scheme with pulse width modulation module and two hysteresis comparators, for the application in single-phase PWM converters to overcome the drawbacks of conventional proportionintegration-based DPC (PI-based DPC), including poor dynamic performance and complexity of tuning PI parameters. According to the outputs of inner-loop power hysteresis controllers, the proposed DPC scheme divides d-q reference frame into four sectors. In each sector, the dynamic power components are estimated to be equivalent as the outputs of PI controllers in PI-based DPC. The proposed DPC scheme provides a new solution of non-linear hysteresis control to achieve fast dynamic performance with constant switching frequency. Additionally, due to inductance parameter mismatch, the effect on powers is analysed in detail, and an inductance parameter on-line estimation method is present and discussed. A comprehensive comparison of conventional table-based DPC, PI-based DPC and the proposed DPC methods has been conducted in this study, including steady-state performance with respect to different factors, and dynamic response under different extreme conditions. The experimental results have verified the effectiveness of the proposed DPC scheme. [ABSTRACT FROM AUTHOR]

Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the effective-seriesresistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

As wearable devices are powered by batteries, they need to consume as little energy as possible. To address this challenge, in this article, we propose a synergistic technique for energy-efficient approximate speech signal processing (ASSP) for wearable devices. More specifically, to enable the efficient trade-off between energy consumption and sound quality, we synergistically integrate an approximate multiplier and a successive approximate register analog-to-digital converter using our enhanced conversion algorithm. The proposed ASSP technique provides ~40% lower energy consumption with ~5% higher sound quality than a traditional one that optimizes only the bit width of SSP. [ABSTRACT FROM AUTHOR]

Accumulated chromatic dispersion (CD) estimation is crucial for frequency-domain equalisation in an optical coherent digital receiver. To solve the problems of small search step size and analogue-to-digital converter (ADC) sampling phase sensitivity from conventional CD searching algorithm, a CD searching method with modified shift parameters and waveforms is proposed in this study. The modified CD searching method allows a much larger search step size and can achieve faster CD estimation with low computational complexity. The performance of the modified CD searching method is also insensitive to ADC sampling phase. On the basis of simulation results, a very low search error probability is confirmed with a search step size of 50 km. About 1 K symbols are found to be enough for dispersion estimation. After the frequency-domain equaliser (FDE) with the estimated dispersion value, the residual dispersion length <30 km can be well compensated with a 9-tap adaptive time-domain equaliser (TDE) with fast convergence. The overall error rate performance of the tunable electrical dispersion compensation is also studied and compared with lumped and distributed optical dispersion compensation for dynamically switched optical networks. [ABSTRACT FROM AUTHOR]

This study presents an architecture to increase the instantaneous dynamic range of multi-carrier wideband digital receivers. The proposed topology includes a directional coupler followed by two parallel analog-to-digital converters and digital signal processing to reconstruct the signal. It will be shown that the proposed technique is able to increase the dynamic range of software-defined radio (SDR) receivers for multiband signals presenting certain statistical patterns. The concept is validated by simulations and measurements of a real SDR front-end receiver for multiband communications scenario, which will demonstrate improvements in the order of 6 dB when compared to existing alternatives. [ABSTRACT FROM AUTHOR]

Design and implementation of a fully table look-up digital pulse-width modulation (DPWM) controller for highfrequency DC-DC buck conversion is presented. The controller comprises a 1 bit analogue comparator, a digital error process unit and a fully table look-up multi-phase DPWM. The interface of analogue-to-digital conversion is performed with the analogue comparator. Moreover, the proposed programmable memory is based on the table look-up multi-phase approach for the functions of the proportional-integral-derivative (PID) compensation, which alleviates the penalty of using large chip-area multipliers. As a result, the approach is very suitable for system-on-a-chip (SOC) implementation. A prototype test chip is realised to validate the mechanism of the proposed architecture. [ABSTRACT FROM AUTHOR]

Analyzes the temporal patterning of vocal behavior by means of a computerized analogue-to-digital conversion system. Time-series regression analysis employed to determine interpersonal influence over the course of the exchange for a variety of temporal parameters; Data revealing that dyads engaged in alternating vocalization to a greater degree than simultaneous vocalization.

This Letter presents a fully integrated bio-system with the property of high sensitivity for electrochemical detection, which can intrinsically measure electrochemical characteristics with cyclic voltammetry. In normal circumstances, ultra-low electrolytes exist in tissue solution, which is difficult to accurately detect the oxidation/reduction signals, limited by the innate circuit and liquid noise. Hence, the conventional topology of the potentiostat circuit is improved and proposed in this Letter to remove the required analogue-to-digital converter (ADC). The overall operational mechanism of the potentiostat behaves like a single-slope ADC, which achieves a compact, easily implemented, and low-noise design. Additionally, the effective capacitance of potentiostat and liquid resistance make an RC integration to further suppress out-of-band noise, thereby enabling the low-electrolyte detection and improving detecting sensitivity. To simulate the low-electrolyte environment, only 0.01 M (M= mol/l) phosphate buffered saline background solution is used and required to demonstrate its feasibility of the concept. The measured results show the sensor chip with high sensitivity to sense resistive variation of electrochemical action in low electrolytes. [ABSTRACT FROM AUTHOR]

A fully-voltage-controlled oscillator (VCO)-based continuous-time (CT) Delta-Sigma (ΔΣ) analogue-to-digital converter (ADC) is reported, implementing second-order noise shaping without any analogue integrators. Traditional power-hungry front-end analogue integrator is replaced by a highly-digital power-efficient VCO-based integrator, which is constructed by a VCO, a phase detector and a charge pump. The quantisation is executed by a VCO-based quantiser with intrinsic noise shaping. Taking advantage of the mostly-digital and high-order structure, a spurious-free dynamic range of 74 dB and a figure-of-merit of 52 fJ/step over a 40 MHz bandwidth are achieved by a 0-2 multi-stage shaping (MASH) demonstration in 40 nm CMOS. [ABSTRACT FROM AUTHOR]

The article focuses on the development of near-infrared sensor measuring muscle oxygen saturation as researched by OBELAB Inc.

A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step. [ABSTRACT FROM AUTHOR]