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A novel inductance simulation circuit employing only two dual‐output voltage‐differencing buffered amplifiers (DO‐VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor‐less realization that provides electronically controllable realized inductance through biasing quantities of DO‐VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO‐VDBAs and does not exhibit instability at high frequencies. The simple and compact metal‐oxide semiconductor (MOS) implementation of the DO‐VDBAs (eight MOS per DO‐VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on‐chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF‐356. [ABSTRACT FROM AUTHOR]

This paper will look at two significant technological developments, one concerning the performance of optical and infrared detector systems, which are now capable of genuine photon counting performance, and secondly a new approach to tackling the problem of adaptive optics when only faint reference stars are available close to the target object. [ABSTRACT FROM AUTHOR]

This paper presents a true‐time delay (TTD) using a commercial 0.13‐μm CMOS process for wideband phased‐array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7‐bit TTD circuit, and a 6‐bit digital step attenuator (DSA) circuit. The T‐type attenuator with a low‐pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time‐delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz–18 GHz. The maximum time delay of 198 ps with a 1.56‐ps step and the maximum attenuation of 31.5 dB with a 0.5‐dB step are achieved at 2 GHz–18 GHz. The RMS time‐delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz–18 GHz. An output P1 dB of <−0.5 dBm is achieved at 2 GHz–18 GHz. The chip size is 3.3 × 1.6 mm2, including pads, and the DC power consumption is 370 mW for a 3.3‐V supply voltage. Because of their electronic beamforming and low SNR, CMOS‐based phased‐array antennas have been widely applied to radar and communication systems. In this paper, the true‐time delay (TTD), as compared to a phase shifter, provides reduced beam squinting and high resolution through a constant time delay over the applied frequency for wideband phased‐array antennas. In addition, the TTD results in a low insertion loss error and a fl at gain performance with a T‐type attenuator and a distributed amplifi er. [ABSTRACT FROM AUTHOR]

The ion‐sensitive field effect transistors (ISFETs), proposed little over 50 years ago, today make the most promising devices for lab‐on‐a‐chip, implantable, and point‐of‐care (POC) diagnostics. Their compatibility with CMOS (Complementary Metal Oxide Semiconductor) technology and the low cost through mass production have been the driving factors so far. Nowadays, they are also being developed in flexible form factors for new applications such as wearables and to improve the effective usage in existing applications such as implantable systems. In this regard, the CMOS ultra‐thin chip (UTC) technology and the bonding by printing are the noteworthy advances. This paper comprehensively reviews such new developments in the CMOS‐compatible ISFETs, along with their theory, readout circuitries, circuit‐based techniques for compensation of the ISFET's instabilities, such as the offset, flicker noise, and drift. The sensing mechanisms and the properties of interface between the electrolyte under test and the metal‐oxide based ion‐sensitive electrodes have been discussed along with a brief overview of the metal‐oxide based pH sensors. An overview of the reported mechanically flexible pH sensors, including ISFETs, is provided and the history of ISFET applications are also covered. Finally, established models that can be used to design flexible circuits are presented, and possible opportunities to use circuit techniques to compensate for mechanical deformation are discussed. [ABSTRACT FROM AUTHOR]

The demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization. [ABSTRACT FROM AUTHOR]

Image sensors, most notably the Charge Coupled Device (CCD), have revolutionized observational astronomy as perhaps the most important innovation after photography. Since the 50th anniversary of the invention of the CCD has passed in 2019, it is time to review the development of detectors for the visible wavelength range, starting with the discovery of the photoelectric effect and the first experiments to utilize it for the photometry of stars at Sternwarte Babelsberg in 1913, over the invention of the CCD, its development at the Jet Propulsion Laboratory, to the high‐performance CCD and complementary metal‐oxide‐semiconductor imagers that are available off‐the‐shelf today. [ABSTRACT FROM AUTHOR]

A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW. [ABSTRACT FROM AUTHOR]

This paper presents a 0.13m CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of --1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper proposes an IEEE 802.15.4m compliant TV white‐space orthogonal frequency‐division multiplexing (TVWS)‐(OFDM) radio frequency (RF) transceiver that can be adopted in advanced metering infrastructures, universal remote controllers, smart factories, consumer electronics, and other areas. The proposed TVWS‐OFDM RF transceiver consists of a receiver, a transmitter, a 25% duty‐cycle local oscillator generator, and a delta‐sigma fractional‐N phase‐locked loop. In the TV band from 470 MHz to 698 MHz, the highly linear RF transmitter protects the occupied TV signals, and the high‐Q filtering RF receiver is tolerable to in‐band interferers as strong as −20 dBm at a 3‐MHz offset. The proposed TVWS‐OFDM RF transceiver is fabricated using a 0.13‐μm CMOS process, and consumes 47 mA in the Tx mode and 35 mA in the Rx mode. The fabricated chip shows a Tx average power of 0 dBm with an error‐vector‐magnitude of < 3%, and a sensitivity level of −103 dBm with a packet‐error‐rate of < 3%. Using the implemented TVWS‐OFDM modules, a public demonstration of electricity metering was successfully carried out. [ABSTRACT FROM AUTHOR]

This paper presents a new analytical approach and experimental verification for the improvement of noise performance in phased-array receivers. For analysis purposes, a multi-channel array system is converted into an equivalent single-channel system, such that the two presents the identical signal and noise powers at the output, respectively. We define an effective gain, noise figure, and signal-to-noise ratio in the equivalent system. Through the proposed approach, the noise performance of the array receiver is analyzed in a general and straightforward manner and then compared to that of each individual array channel. In addition, the phase noise of the array system is analyzed in a rigorous manner, showing its effective reduction by a factor of the array size. The predicted improvement of the noise performance is experimentally confirmed with a CMOS integrated phased-array receiver. [ABSTRACT FROM AUTHOR]

Body implants play a crucial role in clinical applications, encompassing data acquisition, diagnosis, and disease treatment. However, challenges in size, power consumption, and biocompatibility, particularly in brain applications requiring small, battery‐free devices for deep areas, hinder their development. Despite potential advances through simplified, single‐purpose devices, such as recording or stimulation, overcoming the power and biocompatibility issues remains a hurdle. Addressing this, the article introduces an ultrasonically powered light delivery implant (LDI) utilizing lead‐free piezoelectric material (Li0.08K0.46Na0.46) NbO3 to harvest energy from external ultrasonic waves. The prototype includes a piezoelectric cube, a chip fabricated in 180 nm CMOS technology, and a microscale light‐emitting diode (μ‐LED) for optogenetics. Achieving an end‐to‐end efficiency of 0.75%, the LDI holds promise for various optogenetic studies, particularly in animal studies targeting specific brain areas for treating Parkinson's disease. The delivered optical power on the μ‐LED surface, at 14.1 mW mm−2, presents applicability to diverse studies involving specific opsins. [ABSTRACT FROM AUTHOR]

This article presents a solution for the low gain and the poor efficiency of the on‐chip antennas (OCA). The four elements of Quasi‐Yagi‐Uda antennas (QYUA) are introduced based on the diversity technique to reduce the interference between the elements. In addition, these antennas achieve high isolations between them due to the use of reflector for each antenna. The QYUA is selected to improve the radiation properties of the end‐fire radiator in the millimeter‐wave range for on‐chip systems. The proposed MIMO antenna is used for the point to point communications. The complementary metal‐oxide semiconductor with 180 nm standard is used in the antenna design with six metal layers. The QYUA combines three parts (driven element, reflector, and director); the driven consists of two meander lines fed by coplanar‐slot and operates as a dipole, the reflector is an arc likes a semicircle to prevent the back radiation and increase the front to back ratio, and the director is a meander line to directive the radiation into the proposed direction (front end‐fire direction). All MIMO parameters such as envelope correlation coefficient, channel capacity loss, diversity gain, and total active reflection coefficient in addition to the different configurations of the MIMO are presented. All results are verified by computer simulation technology and high‐frequency structure simulator. The contribution of this article is the MIMO antenna design for point to point communications to serve multigiga communications systems with high data rate and high gain. This MIMO system is considered here to solve the problems of OCA designs. [ABSTRACT FROM AUTHOR]

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the lownoise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input P1dB of -11 dBm, and an Rx input IP3 of -2.3 dBm. [ABSTRACT FROM AUTHOR]

This paper presents a switched self-biasing and a tail current-shaping technique to suppress the 1/f noise from a tail current source in differential cross-coupled inductance-capacitance (LC) voltage-controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 μm CMOS process. The measured phase noise is -117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz. [ABSTRACT FROM AUTHOR]

We present an overview of our work on design, development, and demonstration of simple and effective approaches to fabricating solid‐state curved focal plane arrays (CFPAs) that have spawned a novel class of detector arrays. CFPAs can dramatically alter the capability and size of image systems, with an especially high impact in scientific and space applications in terms of science‐instrument size, mass, simplicity, optical performance, and cost. The key to the simplicity of our approaches to curved focal plane arrays, implemented in thick, high‐purity silicon or thinned membrane low‐resistivity substrate detectors is that the curvature of the surface is independent of the VLSI fabrication process of imaging arrays. We present the principles of two approaches, results of fabrication of curved arrays, and results of analysis for limits of curving silicon arrays. New concepts and techniques were also developed as spin offs of this program for extreme curvature FPAs and infrared CPFAs. [ABSTRACT FROM AUTHOR]

New mid‐infrared HgCdTe (MCT) detector arrays developed in collaboration with Teledyne Imaging Sensors (TIS) have paved the way for improved 10‐μ$$ \mu $$m sensors for space‐ and ground‐based observatories. Building on the successful development of longwave HAWAII‐2RGs for space missions such as NEO Surveyor, we characterize the first 13‐μ$$ \mu $$m GeoSnap detector manufactured to overcome the challenges of high‐background rates inherent in ground‐based mid‐IR astronomy. This test device merges the longwave HgCdTe photosensitive material with Teledyne's 2048×2048$$ 2048\times 2048 $$ GeoSnap‐18 (18‐μ$$ \mu $$m pixel) focal plane module, which is equipped with a capacitive transimpedance amplifier (CTIA) readout circuit paired with an onboard 14‐bit analog‐to‐digital converter (ADC). The final assembly yields a mid‐IR detector with high QE, fast readout (>85 Hz), large well depth (>1.2 million electrons), and linear readout. Longwave GeoSnap arrays would ideally be deployed on existing ground‐based telescopes as well as the next generation of extremely large telescopes. While employing advanced adaptive optics (AO) along with state‐of‐the‐art diffraction suppression techniques, instruments utilizing these detectors could attain background‐ and diffraction‐limited imaging at inner working angles <10 λ$$ \lambda $$/D, providing improved contrast‐limited performance compared with JWST MIRI while operating at comparable wavelengths. We describe the performance characteristics of the 13‐μ$$ \mu $$m GeoSnap array operating between 38 and$$ and $$ 45 K, including quantum efficiency, well depth, linearity, gain, dark current, and frequency‐dependent (1/f$$ 1/f $$) noise profile. [ABSTRACT FROM AUTHOR]

We report on our plans to upgrade the detector systems in the 2022–2024 time frame for three of the workhorse instruments (NIRC2, DEIMOS, and NIRES) operated by the W. M. Keck Observatory. The upgrades are done in collaboration with Observatory partner institutions and other Maunakea observatories. The main motivating factors behind these upgrades are to tackle obsolescence of hardware and software components, to boost observing efficiency, to enhance the instrument throughput, and to add new observing functionality. [ABSTRACT FROM AUTHOR]

Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters. [ABSTRACT FROM AUTHOR]

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply. [ABSTRACT FROM AUTHOR]

The conventional computing system has been facing enormous pressure to cope with the uprising demand for computing speed in today's world. In search of high‐speed computing in the nano‐scale era, it becomes the utmost necessity to explore a viable alternative to overcome the challenges of the physical limit of complementary‐metal‐oxide‐semiconductor (CMOS). Towards that direction, the processing‐in‐memory (PIM) is advancing its importance as it keeps the computation as adjacent as possible to memory. It promises to outperform the latencies of the conventional stored‐program concept by embedding storage and data computation in a single unit. On the other hand, the bit storing and processing capability of Akers array provides the foundation of PIM. Again, quantum‐dot cellular automata (QCA) emerges as a promising nanoelectronic to put back CMOS to give fast‐paced devices at the nanoelectronics era. This work presents a novel PIM concept, embedding Akers array in QCA to achieve high‐speed computing at the nano‐scale era. QCA implementation of universal logic utilizing Akers array signifies its processing power and puts forth its potentials. A universal function is considered for testing the effectiveness of the proposed PIM cell. The performance evaluation indicates the efficacy of QCA PIM over the conventional Von Neumann architecture. [ABSTRACT FROM AUTHOR]

A Vernier ring‐oscillator‐based time‐to‐digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151mm2. Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22μW at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors. [ABSTRACT FROM AUTHOR]

A source follower with improved output resistance is proposed. This improvement is achieved using shunt–shunt feedback with the help of a voltage combiner in the feedback loop which helps not only enhancing the gain but achieving reduced distortion due to improved isolation. A high‐performance Sallen–Key biquad is implemented using this improved source follower and two capacitors which offer 29.3 MHz of bandwidth and almost 50 dB of stopband attenuation with the power of 2.3 mW. A fourth‐order Chebyshev low‐pass filter prototype is designed with a cascade of two such biquads in 45 nm complementary metal–oxide–semiconductor (CMOS). A cut‐off frequency of 12.4 MHz is obtained with a stopband rejection of more than 83 dB. The power dissipation of the filter is 5.1 mW, at 1.2 V supply, and achieves an in‐band third‐order intercept point of +26.8 dBm. The in‐band input‐referred noise is 3.4(uV/Hz), resulting in a dynamic range of 78.1 dB. [ABSTRACT FROM AUTHOR]

In this study, a novel level shifted version of flipped voltage follower (FVF) cell, which provides efficient class‐AB operation, is presented. The level shifter is used to increase the swing of the FVF cell. In the proposed circuit, a bulk‐driven metal–oxide–semiconductor field effect transistor is used as a current source to improve the sourcing capability and symmetrical slew rate for the class‐AB operation. The circuit has a high‐input/‐output swing of 1.01 V/0.80 V, wide bandwidth of 751 MHz and low‐output resistance of 107 Ω. The proposed circuit has been designed and simulated in a Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm complementary metal–oxide–semiconductor technology. The post‐layout simulation results have also been presented to demonstrate the performance of the proposed circuit. [ABSTRACT FROM AUTHOR]

This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works. [ABSTRACT FROM AUTHOR]

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high‐throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT. [ABSTRACT FROM AUTHOR]

The authors propose an asynchronous‐logic (async) quasi‐delay‐insensitive (QDI) autonomous signal‐validity half‐buffer (ASVHB) realisation approach for low power sub‐threshold operation (VDD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine‐grained gate‐level method, which propagates data through a single‐cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static‐logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub‐threshold operation. They compare their ASVHB realisation approach against the competitive reported weak‐conditioned half‐buffer (WCHB) and pre‐charged half‐buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require ∼2.1 × and ∼1.9 × more transistors than the ASVHB library cells. With respect to a 3‐stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 × and 1.5× more transitions per‐cycle than the ASVHB pipeline. They design an async 32‐bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm CMOS process). Their ASVHB ALU occupies 0.092 mm2, and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require ∼1.7 × and ∼1.4× more transistors, respectively, than their design. At the sub‐threshold voltage of VDD = 0.2 V, the WCHB and PCHB counterparts dissipate ∼1.7× and ∼2.6× more energy, respectively, and are, respectively, ∼0.95× and ∼0.73× slower throughput. [ABSTRACT FROM AUTHOR]

A new complementary metal oxide semiconductor (CMOS) relaxation oscillator featuring with high linearity and low‐jitter is presented in this study. The high linearity between the frequency and control current is achieved by adopting the floating capacitor and the independent charged and discharged loops. The low‐jitter performance is gained because of that the voltage across the floating capacitor is larger than the conventional oscillator. The proposed circuit is compatible with standard CMOS process and one test‐chip with typical frequency of 6.66 MHz was implemented in the 0.5 μm (bipolar–CMOS–double‐diffused metaloxide semiconductor (DMOS)) (BCD) process. The measured results show that <0.86% non‐linearity in the current–frequency transfer function from 1 to 6.66 MHz without trimming. The cycle‐to‐cycle jitter was <112 ppm. [ABSTRACT FROM AUTHOR]

Variations of low‐frequency noise including flicker and Lorentzian spectra are the dominant source of variation of noise equivalent power (NEP) for terahertz detectors using diode‐connected N‐type MOS (NMOS) transistors. The low‐frequency noise of Schottky diodes fabricated in the same CMOS process as the NMOS detectors are dominated by generation and recombination noise. At 1 MHz modulation frequency, the noise of Schottky barrier diodes (SBDs) and its variation are ∼2× lower than those of diode‐connected NMOS transistors. It should be possible to reduce the variation of NEP by ∼2× using Schottky diode detectors modulated at 1 MHz. [ABSTRACT FROM AUTHOR]

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-µm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 µW from a 1.2-V power supply. [ABSTRACT FROM AUTHOR]

A 60 GHz down‐conversion mixer for a superheterodyne receiver with an IF frequency of about 12 GHz is reported. On the basis of the double‐balanced Gilbert cell, the mixer comprises two series LCR networks to enlarge the IF bandwidth (BW) and a cross‐coupled pair used as positive feedback to the raise conversion gain (CG) at the load stage. By adjusting the bias of the cross‐coupled pair, the mixer features a variable CG. The mixer core only consumes 2.8 mA from a 1.2 V supply when the cross‐coupled pair is turned off, whereas the corresponding a 3 dB IF BW is from 6.5 to 17.5 GHz with a 3 dB CG, which is believed to be the widest IF BW ever reported for a 60 GHz down‐conversion mixer with an IF frequency of about 12 GHz. The CG can be enhanced by driving the cross‐coupled pair, which consumes another 2.4 mA, i.e. 5.2 mA in all for the mixer core. The CG will reach 7.5 dB and the corresponding 3 dB IF BW is from 8 to 16 GHz, where the CG and BW product against power consumption is also believed one of the best results ever reported for a 60 GHz down‐conversion mixer with IF frequency of about 12 GHz. [ABSTRACT FROM AUTHOR]

A low‐phase‐noise transformer‐based gate‐coupled quadrature voltage‐controlled oscillator (TGC‐QVCO) using 0.13 μm CMOS technology is presented. The TGC‐QVCO consumes 7 mW at 1 V power supply with 18% frequency tuning. The measured phase noise at 1 MHz offset varies from about −122 to −119 dBc/Hz for frequency tuning from 1.34 to 1.6 GHz. The achieved figure of merit (FoM) is 179 dB and the chip area is 800 × 900 μm2. [ABSTRACT FROM AUTHOR]