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The filter on monolithic LSI for communication and measurement is realized by the digital signal processor (DSP) or the switched capacitor (SC) circuit. In the analog-digital interface, high-speed processing, applications requiring low power consumption operations, and low cost, SC circuits will be superior to the DSP circuits. The authors devised the SC circuit called parallel cyclic-type, which can further enhance the high-frequency and low power-consumption operation. The single-rate FIR and IIR filters have been proposed using the circuit. In this paper, the high frequency and low power-consumption FIR and IIR decimation filters using the SC parallel cyclic-type circuits are proposed. The effects of the finite gain bandwidth (GB product) of the operational amplifier and of the parasitic capacitance on the filter characteristics are analyzed. The proposed filters and the decimation filter by Franca et al. are constructed using discrete elements and the characteristics are examined. The characteristics are compared with the computer simulations. It is verified as a result that the proposed decimation filter has a much better performance than the filter by Franca et al. [ABSTRACT FROM AUTHOR]