Search

This article presents a study on the improvement of the gate robustness and reliability of p‐GaN gate high‐electron‐mobility transistors (HEMTs) by doping profile engineering and by performing a thermal treatment. The reduction of the p‐doping concentration at the Schottky interface using a graded magnesium (Mg) profile in the p‐GaN layer and introducing a top Si‐GaN cap layer is proposed, combined with a high‐temperature anneal step after the gate patterning. The results show that the proposed approach enhances the gate breakdown voltage, reduces the gate leakage current, and increases the time to failure under constant voltage stress, while ensuring stable dynamic behavior and off‐state leakage performance under high‐voltage stress. [ABSTRACT FROM AUTHOR]

To investigate the defects from the gate regrowth process, samples with and without regrowth p‐GaN process are fabricated by metalorganic chemical vapor deposition (MOCVD). The DC characteristics indicate larger gate leakage (Igs) between the GaN channel and the p‐GaN gate in the regrowth sample than in the nonregrowth counterpart. In addition, significant Si/O impurities are introduced by the regrowth process at the interface between channel and regrown AlGaN barrier. The low‐frequency noise (LFN) measurement and deep‐level transient spectroscopy (DLTS) are further carried out to investigate the defectivity at the AlGaN barrier and channel interface, giving a 2–3 times higher border trap density in the AlGaN barrier (depth ≈5 nm from the channel interface) and a 10 times increase in interface trap density at the channel interface, corresponding with a band of shallow levels E3 = Ec–0.02–0.15 eV. Three additional bulk traps E2/E5 (Ec–0.8 eV, σn=5×10−15 cm2 / Ec–0.17 eV, σn=5×10−22 cm2) and E4 (Ec–0.23 eV, σn=5×10−19 cm2) are also found in the regrowth and nonregrowth samples, respectively. Their possible spatial locations and origins are discussed. [ABSTRACT FROM AUTHOR]

We investigate the DC and dynamic characteristics of AlGaN/GaN Schottky barrier diodes (SBDs) and the diodes with a gated edge termination (GET-SBD) fabricated on unintentional doped (UID) and carbon-doped AlGaN buffers. The off-state characteristics of diodes fabricated on UID buffer are dominated by buffer leakage and buffer breakdown voltage (BV) at higher reverse voltage ( [ABSTRACT FROM AUTHOR]

In this work, we have systematically investigated the technique of low-temperature AlN interlayer in MOCVD growth of double heterojunction high-electron-mobility transistors buffer stacks on 200 mm Si (111) substrates. We have demonstrated that a continuous compressive stress can be maintained by insertion of interlayers which compensated a large tensile stress during cooling for a thick buffer. This eventually led to a low wafer bow and a good surface quality that enabled wafers with full device stack meeting the specifications for processing in our 200 mm CMOS pilot line. We also demonstrated at both forward and reverse bias conditions a significantly improved vertical buffer breakdown voltage (which is defined at a leakage current of 1 µA/mm² in the present work) of >500 V at 25 °C and >300 V at 150 °C, respectively. [ABSTRACT FROM AUTHOR]

In this work we report on the three dominant trapping mechanisms affecting the dynamic performance of a double-heterostructure GaN-based MIS-HEMT grown on silicon substrate. In the OFF-state, with high drain voltage and pinched-off 2DEG, the dominant mechanism is the charge-trapping in the gate-drain access region caused by the transversal drain-to-substrate potential. This effect causes the dynamic increase of the ON-resistance, and is positively temperature-dependent, thus of great concern for high-temperature operation. In the SEMI-ON-state, due to the presence of high VDS and relatively high IDS, an additional trapping mechanism emerges, involving the injection of hot electrons from the 2DEG into trap states located in the GaN-buffer or in the AlGaN barrier. This mechanism, critical in hard-switching operations, affects both the ON-resistance and the VTH. Finally, when the gate is positively biased (gate overdrive state) trapping of electrons happens in the gate dielectric layer(s), leading to strong metastable VTH instabilities. [ABSTRACT FROM AUTHOR]

AlGaN/GaN/AlGaN double heterojunction high-electron-mobility transistors were grown on 200 mm Si (111) using metalorganic chemical vapor deposition. The Al composition of AlGaN barrier varied from 20 at% to 30 at% and thickness from 10 nm to 20 nm. In some structures, a 1 nm AlN interlayer was inserted between AlGaN barrier and GaN channel. The as-grown wafers were proven to be of high material quality and the layer thickness were well controlled to the target values. A buffer break down voltage of over 700 V were obtained for all grown wafers. Compared to their counterparts without AlN interlayer, structures with AlN interlayer showed a much lower and more uniform two-dimensional electron gas sheet resistance. With the presence of AlN interlayer, the sheet resistance was much less sensitive towards variations in AlGaN barrier composition and thickness. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

This works presents a comparison of several different AlGaN/GaN powerbar designs, with a total gate width of 9mm, with the goal to minimize the total gate resistance. Analytical models were developed for the interconnect parasitics to aid in the design phase. The different power transistor topologies were fabricated in a GaN-on-Si MISHEMT technology. Measurements on the fabricated transistors showed a good agreement between the analytical models and the measurements. Furthermore, the modelling framework allowed us to design power transistors that reached the goal of reducing the gate resistance while having minimal impact on other characteristics. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

AlGaN/GaN Schottky barrier diodes (SBDs) have been fabricated on GaN-on-Si wafers (8-inch) with Au-free CMOS compatible technology. Two types of Edge Terminations have been investigated to suppress the leakage current with the conventional AlGaN/GaN Schottky Barrier Diodes fabricated on the same wafer as a reference. The External Edge Terminated-SBD (EET-SBD) shows a trend of reduction in leakage current by scaling down the spacing between the edge termination and the Schottky contact. By embedding the edge terminations inside the anode region named Gated Edge Terminated-SBD (GET-SBD), four orders of magnitude reduction in leakage current has been observed experimentally compared with the reference. Furthermore, anode recess was performed and its influences on both on- and off-state characteristics were studied. The recessed EET-SBD shows lower leakage current than the non-recessed one. The forward voltage drop in EET-SBD appears to be degraded by recess. The recessed GET-SBD features the lowest leakage (1 µA/mm at VAC of -600 V) and improved on-state performance (with VF of 1.15 V). With Anode-to-Cathode distance ( LAC) of 10 µm, a breakdown voltage over 600 V in all three architectures has been achieved in both recessed and non-recessed wafers. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]