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A continuous‐time offset cancelation and gain calibration strategy is proposed for open‐loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide‐bits digital processor for offset and gain‐error correction. Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input‐referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Post‐layout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14‐bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB. [ABSTRACT FROM AUTHOR]

Summary: A 12‐Gb/s 0.18‐μm complementary metal oxide semiconductor (CMOS) serial link transceiver with embedded clock signal in data stream using dual‐mode pulse amplitude modulation is presented. The 6‐bit data and the clock signal are both transferred through the same transmission channel. In the proposed modulation technique, the clock signal is easily recovered using a conventional phase‐locked loop without any complex encoders in the transmitter circuit. The transmitter includes multiplexers, an output driver, and pre‐emphasis circuitry with 127‐mW power consumption. The receiver is composed of a phase‐locked loop for clock recovery and demodulator blocks for data recovery, and it dissipates 45 mW of power. [ABSTRACT FROM AUTHOR]

This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works. [ABSTRACT FROM AUTHOR]

In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high‐speed pipelined analogue‐digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non‐linearity error and 1.2 Vp‐p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal‐oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm2 of die area. Simulations are performed in HSPICE using level 49 models. [ABSTRACT FROM AUTHOR]

A novel topology for a high gain two‐stage amplifier is proposed. The proposed circuit is designed in a way that the non‐dominant pole is at output of the first stage. A positive capacitive feedback around the second stage introduces a left half‐plane zero, which cancels the phase shift introduced by the non‐dominant pole, considerably. The dominant pole is at the output node, which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18 µm complementary metal‐oxide‐semiconductor process. It consumes 0.86 mW power from a 1.8 V power supply and occupies 3038.5 µm2 of chip area. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5 pF capacitive load. Also low frequency common‐mode rejection ratio and positive power supply rejection ratio are 127 and 83.2 dB, respectively. They are 24.8 and 24.2 dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in process corners and also the presence of a mismatch. [ABSTRACT FROM AUTHOR]