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Summary: In this paper, we investigate the application of the direct ΔΣ receiver (DDSR) concept in a mixer‐first architecture. Specifically, we analyze the degrading effects of quantization noise (Qn) upconversion on DDSR sensitivity, which is a major concern in mixer‐first DDSR architecture. We demonstrate that with the chosen approach, the mixer‐first architecture is suitable for the DDSR despite the potential challenges arising from Qn upconversion. A systematic modeling and understanding of Qn upconversion effects is presented, which lead to simple design guidelines. The results demonstrate that a first‐order low‐pass Qn filtering is sufficient in most cases for mixer‐first DDSR implementations. Based on analytical results, we design a transistor‐level mixer‐first DDSR by merging the functionality of N‐path capacitors both as channel select and Qn filters. Simulations performed in a 28‐nm complementary metal‐oxideŰsemiconductor (CMOS) process show a mere 1.5‐dB degradation from maximum signal‐to‐noise and distortion ratio (SNDR) for the worst‐case scenarios arising from Qn upconversion effects, validating the chosen approach. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of −1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO. [ABSTRACT FROM AUTHOR]