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Summary: In this paper we describe an FPGA implementation of the Scale Invariant Feature Transform (SIFT) algorithm. The FPGA is required as its a lightweight device which makes it ideal for vision‐guided hybrid neuro‐prostheses utilised for upper limbs replacement. SIFT point detection is needed for computation of coordinates of the object‐to‐grasp in a wearable multi‐camera system. A modified SIFT algorithm is proposed and an implementation of it into C/C++ language on Xilinx ZCU102 FPGA board. The proposed hybrid hardware/software solution is compared to other hardware or hybrid implementations of the SIFT algorithm and with the baseline software detector OpenSIFT. The algorithm optimised for FPGA gives an average precision of 0.84 and the average recall of 0.94 in SIFT‐point detection compared to the baseline. The proposed solution has lower dissipated power than other solutions like CPU or GPU, and it has better computational speed. This solution allows for processing medium‐sized images in real‐time with low power consumption. [ABSTRACT FROM AUTHOR]

SUMMARY In the paper, an field-programmable gate array (FPGA)-based framework is described to efficiently accelerate unstructured finite volume computations where the same mathematical expression has to be evaluated at every point of the mesh. The irregular memory access patterns caused by the unstructured spatial discretization are eliminated by a novel mesh node reordering technique, and a special architecture is designed to fully utilize the benefits of the predictable memory access patterns. In the proposed architecture, a fixed-size moving window of the input stream of the reordered state variables is cached into the on-chip memory and a pipelined chain of processing elements, which gets input only from the fast on-chip memory, is used to carry out the computations. The arithmetic unit (AU) of the processing elements is generated from the data flow graph extracted from the given mathematical expression. The data flow graph is partitioned with a novel graph partitioning algorithm to break up the AU into smaller locally controlled parts, which can be more efficiently implemented in FPGA than the globally controlled AU. The proposed architecture and algorithms are presented via a case study solving the Euler equations on an unstructured mesh. On the currently available largest FPGA, the generated architecture contains three processing elements working in a pipelined fashion to provide one order of magnitude speedup compared with a high performance microprocessor and three times speedup compared with a high performance graphics processing unit. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]