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Effective interface engineering techniques in III-nitride heterojunction power devices, aiming at yielding high VTH stability in insulated-gate devices and suppressed current collapse in high-voltage switching operation, are of critical significance to enhance device performance and reliability. In this work, we present an interface enhancement technology featuring in situ low-damage NH3/Ar/N2 pre-gate plasma treatment prior to the ALD-Al2O3 deposition for high-performance III-nitride MIS-HEMTs. It is manifest that this technology can effectively remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the III-nitride surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS-heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including a small subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T dispersions in the C- V characteristics, and low interface trap density of ∼1 × 1012-6 × 1012 cm−2eV−1. Cross-sectional TEM micrograph of the Al2O3/III-nitride gate stack with a monocrystal-like nitridation interfacial-layer (NIL). [ABSTRACT FROM AUTHOR]

The GaN-to-Si vertical conduction mechanisms on a low resistivity p-type (111) Si substrate under high-voltage operation are investigated using the temperature-dependent high-voltage C-V characterization and device simulation. It is found the deep depletion and weak inversion in Si will result in a high electric field at the GaN/Si interface and induce the impact ionization of Si. The generated electrons will be injected into GaN buffer layer, fill in buffer traps and act as free carriers in GaN, eventually leading to considerable vertical leakage in the AlGaN/GaN-on-Si structures. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The threshold voltage ( VT) instability of metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) is investigated. In the enhancement-mode AlGaN/GaN MIS-HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi-static I - V (current-voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT-instability is attributed to the traps located at the dielectric/III-nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi-static measurement can only reflect slow traps (deep traps), and is more accurate for VT-instability evaluation. In addition, the existence of bulk traps is implied by a slow time-dependent shift of VT under large gate bias. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]