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The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary‐based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries. [ABSTRACT FROM AUTHOR]

This study presents a very‐large‐scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high‐throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB. [ABSTRACT FROM AUTHOR]

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier‐based double throughput MAC. [ABSTRACT FROM AUTHOR]

H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual‐standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard. [ABSTRACT FROM AUTHOR]

This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory accesses. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new approach through the reuse of the previously-search data in two dimensions. Our new architecture in this paper is an extension from our previous work such that we reuse the previously-searches area not only between two consecutive columns but also between two consecutive rows, so as to entirely remove redundant memory accesses. Experimental results show that our architecture of increased area by 81% can reduce 98% of memory accesses. Total power reduction is 86% in power estimation by SPICE model. [ABSTRACT FROM AUTHOR]

Currently, considerable research is being performed on multiplierless structural methods for fixed coefficient filters, but not much research has been done on structural methods for creating adaptive filters whose coefficients vary with time. A few multiplierless structural methods have been proposed as structural methods using distributed arithmetic, but these conventional methods use particular encoding for input signals, and thus experience very high levels of degradation in their convergence characteristics. The authors improve significantly the convergence characteristics by generalizing this method using a new two's complement method. In addition, the authors propose a VLSI architecture not considered in conventional methods and perform VLSI evaluations of their structural method. The results show that the authors' proposed method can dramatically reduce power consumption and hardware requirements while sustaining high performance and very low latency compared to structural methods that use a multiplier. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 84(5): 1–12, 2001 [ABSTRACT FROM AUTHOR]

A hardware‐oriented lossless electrocardiogram compression algorithm is presented for very large‐scale integration (VLSI) circuit design. To achieve high performance and low complexity, a novel prediction method based on the fuzzy decision and particle swarm optimiser (PSO) was developed. The accuracy of prediction was advanced efficiently by using the PSO algorithm to find the optimal parameters, which provided 64 situations for the fuzzy decision. Moreover, a novel low‐complexity and high‐performance entropy‐coding algorithm based on Huffman coding was developed, which used one limited Huffman coding to encode a main region and five‐region codes to encode the extending regions. The average compression rate of the whole MIT‐BIH Arrhythmia database was up to 2.84 by combing the proposed fuzzy‐based PSO prediction and Huffman region entropy‐coding techniques. The VLSI architecture contained only a 1.9 K gate count and its core area was 5965 μm2 synthesised using a 90 nm CMOS process. It consumed 201 μW when operating at a 200 MHz processing rate. Compared with previous low‐complexity designs, the average compression rate is not only improved by more than 6.4% but also reduced the gate count by at least 8.2%. [ABSTRACT FROM AUTHOR]

A VLSI architecture of a context adaptive binary arithmetic coding (CABAC) entropy codec for high‐efficiency video coding (HEVC), the next generation video coding standard, is presented and analysis of its performance in terms of effective processing throughput, i.e. bin/s, is provided. For high throughput, the architecture is designed to process up to two regular bins per unit time while minimising pipeline stall due to inherent dependencies of CABAC through various optimisations including context forwarding and speculative decoding. The experiments show that the effective throughput is achieved up to 1.60 bins or 1.41 bits per cycle, which corresponds to 469.5 Mbit/s at the operating frequency of 333 MHz, under practical video coding environments. [ABSTRACT FROM AUTHOR]

An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs. [ABSTRACT FROM AUTHOR]