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Summary: We propose a novel CMOS differential voltage‐controlled equivalent active resistor based on a modified common‐source cross‐coupled pair. The equivalent resistance exhibited by the circuit can be tuned to be either positive or negative through the tail current, which is controlled by a bias voltage. The complete cell comprises four transistors, two resistors in addition to the bias voltage, and tail current source. Application to the design of oscillators is demonstrated by theoretical analysis, circuit simulations, and verified experimentally through measurements on prototypes implemented using discrete transistors. In this work, we propose a novel tunable negative or positive differential resistance implemented using four transistors, which offers an advantage over the conventional cross‐coupled differential pair. The advantage being that the equivalent resistance exhibited by the circuit can be tuned to be either negative or positive through a tail current as well as via a bias voltage. Its linearity and range of operation are examined, and applications to oscillators are demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper reports the analyses of the inductive degeneration, noise filter, and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A 50 GHz cross-coupled differential-pair oscillator with a high-Q active inductor in the LC tank has been designed and fabricated in 65 nm bulk complementary metal-oxide semiconductor (CMOS) technology. The principle of operation is explained and a complete theoretical study is carried out. The analytical expressions for the open loop transfer function, oscillation frequency, start-up condition, tank impedance, and phase noise are derived. The results of the analytical study are compared with those obtained by SpectreRF simulations in the Cadence design environment. Measurement results of the stand-alone mm-wave active inductor show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally the implementation of high-Q active inductors operating at the millimeter waves in CMOS technology. The measurement results of the oscillator show a phase noise of −85 dBc/Hz at 1 MHz frequency offset from the carrier when the active inductor is switched off and −91 dBc/Hz when it is switched on, leading to a phased noise reduction of 6 dB. [ABSTRACT FROM AUTHOR]

This paper reports a novel oscillator circuit topology based on a transformer-coupled p-network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root-locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed-form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer-coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. [ABSTRACT FROM AUTHOR]

This paper presents a 67GHz LC oscillator exploiting a three-spiral transformer and implemented in 65nm bulk complementary metal-oxide-semiconductor technology by STMicroelectronics. The three-spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise ( PN) equal to −96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption ( PC) equal to 19.2 mW and figure of merit ( FOM) equal to −179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to −88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; PC equal to 3.6 mW and FOM equal to −179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal-oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd. [ABSTRACT FROM AUTHOR]