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In this paper, the clamping effect introduced by several diode-based configurations used for the implementation of the high-value resistors in quasi-floating-gate circuits is analyzed and characterized. In contrast to previous approaches where a parasitic diode is treated as a simple high-value resistor reducing the circuit complexity, in this case the analysis considers the diode behavior which leads to a clamping circuit. This clamping circuit introduces an unwanted amplitude-dependent offset voltage, which affects the performance moving the quiescent point at the quasi-floating-gate transistors. A new anti-parallel diode configuration for quasi-floating-gate applications is proposed in this work, which eliminates this unwanted offset voltage. The proposed design is validated using simulations and experimental data in a CMOS 0.35- μ m technology. [ABSTRACT FROM AUTHOR]

The performance of processors in a distributed system can be measured by parameters such as bandwidth, storage capacity, work capability, reliability, power limitations, years of usage, among others. Each processor defines its preference based on these parameters. The preference represents an indicator of the quality of service that a processor can provide. An algorithm that follows a preference-based approach uses the preference of the processors to make decisions. In this paper we introduce a randomized self-stabilizing leader election algorithm for preference-based anonymous trees. Our algorithm assures that the processor with the highest preference in the system is always selected as the leader; moreover, it is able to solve symmetric configurations where each preference is the same. We prove that our algorithm has an optimal average time complexity and we also performed simulations to illustrate the average performance of the algorithm. [ABSTRACT FROM AUTHOR]

In this paper we present a simulation of an acyclic n×n DR-Mesh on an n×n LR-Mesh. The simulation is efficient in regards to size since both models use the same number of processors. The worst execution time for this simulation is O(n2) time, but we demonstrate that its average execution time is O(logn). The fastest existing simulation takes O(logn) time, but it uses an extremely large number of processors. On the other hand, the most efficient simulation in terms of size takes O(log2n) time with O(n4/log2n) processors. Both of the existing simulations are for the unrestricted DR-Mesh. This paper provides an important step towards efficiently simulating the unrestricted DR-Mesh on weaker models such as the R-Mesh and the LR-Mesh. [ABSTRACT FROM AUTHOR]