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A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6-4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process. [ABSTRACT FROM AUTHOR]

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology. [ABSTRACT FROM AUTHOR]

An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation. [ABSTRACT FROM AUTHOR]

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched di®erential pairs. Duty cycle of output di®erential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05mm² active area in a 0.18μm CMOS technology. [ABSTRACT FROM AUTHOR]

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 ¡im CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 /¿m technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm-0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30-70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30-70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle. [ABSTRACT FROM AUTHOR]

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity. [ABSTRACT FROM AUTHOR]

A novel high speed linear tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode is proposed. Using this OTA, we construct a high speed fuzzifier and implement trapezoidal/triangular functions with all parameters (slope, width, and position) independently and continuously tunable, and excellent for low voltage applications. Computer simulations verify the performance of this circuit, showing high speed (up to 100 MHz) and a high support range (up to 2.5 V). [ABSTRACT FROM AUTHOR]