23 results on '"Guitard, Nicolas"'
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2. Next Generation SiGe HBTs for Energy Efficient Microwave Power Amplification (Invited)
3. Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes
4. Recovery of Intrinsic Heterojunction Bipolar Transistors Profiles by Neural Networks
5. ESD Protection Based on Stacked SCRs With Adjustable Triggering Voltage for CMOS High-Voltage Application
6. Kinetic Monte Carlo for Process Simulation: First Principles Calibrated Parameters for BO2
7. SOI CMOS and SiGe BiCMOS Technologies for RF and mmW Applications
8. Smart Way to Adjust Schottky Barrier Height in 130 nm BiCMOS Process for sub-THz Applications
9. Scalable Analytical Model of 1.7 THz Cut-off Frequency Schottky Diodes Integrated in 55nm BiCMOS Technology
10. Characterization of Heated Ion Implantation for non Amorphizing Conditions and Correlation with Kinetic Monte Carlo Simulations
11. Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology
12. ESD protection structure enhancement against Latch-Up issue using TCAD simulation
13. Improved ESD Protection in Advanced FDSOI by SON/Bulk Co-integration - EOS/ESD symposium 2010, september, Anaheim, CA USA
14. Caractérisation de défauts latents dans les circuits intégrés soumis à des décharges électrostatiques
15. OBIC technique for ESD defect localization : Influence of the experimental procedure
16. Applications of various optical techniques for ESD defect localization
17. Different failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure
18. EOS characterization methodology applied to disable feature of ESD power clamps.
19. Are artificial tracers conservative in argillaceous media? The Tournemire claystone case
20. Optimizing Pulsed OBIC Technique for ESD Defect Localization
21. Optimizing pulsed OBIC technique for ESD defect localization
22. Investigation of product burn-in failures due to powered NPN bipolar latching of active MOSFET rail clamps.
23. Point to point ESD protection network, a flexible and competitive strategy demonstrated in advanced CMOS technology.
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