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In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model. Index Terms--Flip-flop, FPGA, low power and low die area, LUT, MRAM, nonvolatile, run-time reconfiguration, SOPC.

A model on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs is reported. It is found that the key to accurate modeling is the precision of parameters extraction, and therefore a method enabling this extraction in the triple-well environment is proposed.

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance, and nonvolatility. However, the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g., 64). This leads to significant improvement of data density (e.g., \1.75\,F^2 /bit). Special techniques are also presented to address the sneak currents and low-speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using an STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed, and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture. [ABSTRACT FROM PUBLISHER]

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area. [ABSTRACT FROM PUBLISHER]

This paper details the modeling of a one-transistor dynamic random-access memory (1TDRAM) based on an independent double-gate device. A pseudo-2-D compact model of memory operations and dynamic behavior of data retention is proposed. The physical mechanisms involved are calculated through the accumulated charge in the body modulated by quantum effects related to thin silicon films. The resulting currents from programming operations are detailed. We consider current leakages, generation/recombination, and band-to-band tunneling parasitic effects for data retention. [ABSTRACT FROM AUTHOR]

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its non-volatility and high write/read speed allow to power down completely the logic blocks in "idle" states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits. [ABSTRACT FROM AUTHOR]