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The dc current gain of InP-GaInAs heterojunction bipolar transistors with varying base thickness and composition were examined. The reduction of base transit time due to hot electron injection is observed in devices with thin uniform bases using a simple two-parameter Monte Carlo simulation.

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base [1]. The expressions for the base--collector capacitances are valid for both the hybrid-[pi] and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy. Index Terms--Heterojunction bipolar transistors (HBTs), parameter extraction, small-signal equivalent circuit.

Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13-\mu\m SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than -\12-dBm input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71–76 GHz) and higher band (HB) (81–86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission. [ABSTRACT FROM PUBLISHER]

Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in diverse computing domains, directly and indirectly leading to diminishing performance returns as the many-core era is approaching. Novel interconnect technologies could help revert this trend by offering, among others, improved broadcast support, even in large-scale chip multiprocessors. This article outlines the prospects of wireless on-chip communication technologies pointing toward low-latency (a few cycles) and energy-efficient broadcast (a few picojoules per bit). It also discusses the challenges and potential impact of adopting these technologies as key enablers of unconventional hardware architectures and algorithmic approaches, in the pathway of significantly improving the performance, energy efficiency, scalability, and programmability of many-core chips. [ABSTRACT FROM PUBLISHER]