Search

We extract the electric properties of border traps with long time constant in low-pressure chemical vapor deposition (LPCVD) Si3N4/GaN/AlGaN/GaN metalâ€"insulatorâ€"semiconductor (MIS) structure using quasi-static capacitance voltage method. The energy and depth distribution of the border traps is calculated based on the analysis of energy band diagram and charging dynamic of border traps in the MIS structures. With this method, it is found that LPCVD Si3N4/GaN/AlGaN/GaN MIS structure have a high density of border traps in the order up to 1021 cmâˆ'3 eVâˆ'1 located at energy level between E C,GaN âˆ' 0.04 eV and E C,GaN âˆ' 0.66 eV with distance of 1.0â€"4.2 nm from the Si3N4/GaN interface. Microstructure analysis suggests that the high density of border traps is possibly correlated to the oxygen content at the Si3N4/GaN interface. Meanwhile, the proposed method is also suitable for MIS or metal-oxide-semiconductor structure on other semiconductors, providing another powerful tool to analysis the physical properties of border traps. [ABSTRACT FROM AUTHOR]

Junction termination extension (JTE) is a mature edge termination structure in Si and SiC power devices, but remains a technical challenge in GaN due to lack of mature selective area doping technique. In this work, GaN vertical p-n diodes with Hydrogen-Modulated Step Graded JTE (HMSG-JTE) are realized by gradually enlarging photolithography windows for hydrogen plasma treatment and controlled thermal diffusion of hydrogen in p-GaN. HMSG-JTE leads to a gradually decreasing hole distribution outwards from the main junction, which laterally spreads the electric field and mitigates the electric field peak under reverse bias. Consequently, the breakdown voltage of vertical GaN p-n diode is successfully boosted from 661 V (with hydrogen-plasma-based edge termination) to 1489 V with HMSG-JTE. [ABSTRACT FROM AUTHOR]

In this letter, we report a quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility. The reduction of dislocation is realized by inserting a thin layer with high density of Ga vacancies to promote the dislocation bending. The dislocation density is ${1.6}\times {10}^{{8}}$ cm−2 with a GaN drift layer thickness of $4.5~\mu \text{m}$. The fabricated prototype GaN SBD delivers a high on/off current ratio of $10^{{10}}$ , a high forward current density of 1.6 kA/cm2@3 V, a low specific on-resistance of 1.1 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , and a low ideality factor of 1.23. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron-mobility transistor (HEMT) based pH sensors have the advantages of fast response and high stability, and can be used in harsh environments. This paper presents a pH sensor based on a planar dual-gate AlGaN/GaN HEMT cascode amplifier, which can increase the pH sensitivity for about 45 times from 45 mV/pH to 2.06 V/pH with linearity of 1.27%. The results indicate that it is possible to improve the pH sensitivity at the origin of detecting instead of the subsequent complex amplifier circuits. The proposed device has also shown the capacity to adjust the sensor’s sensitivity by changing the gate voltage and the resistance values for various pH ranges of different measuring requirements. [ABSTRACT FROM AUTHOR]

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al)GaN interface and the effect on threshold voltage (${V}_{\text {TH}}$) instability and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) ${C}$ – ${V}$ (QSCV), time-of-fly (TOF) stress/measure, and QS ${I}_{\text {D}}$ – ${V}_{\text {DS}}$ methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better ${V}_{\text {TH}}$ stability and lower ${R} _{ \mathrm{\scriptscriptstyle ON},\text {D}}/{R} _{ \mathrm{\scriptscriptstyle ON},\text {S}}$ ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors. [ABSTRACT FROM AUTHOR]

In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures. [ABSTRACT FROM AUTHOR]

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability. [ABSTRACT FROM AUTHOR]

For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage ( V{\textbf {ON}} of 0.68±0.13 versus 0.65±0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage. [ABSTRACT FROM AUTHOR]

In this letter, a gate recessed normally-off GaN metal–oxide–semiconductor high-electron-mobility transistor on silicon substrate is fabricated using AlN/Si3N4 as the passivation layer. The thin AlN layer serves the dual role of protecting the gate channel region from direct plasma bombardment during the RIE Si3N4 removal and passivating the surface states in the access region. As a result, the effective carrier mobility in the normally-off channel is found to improve from the 568 cm2/ \text V\cdot \text s in conventional Si3N4 passivation process to a high value of 1154 cm2/ \text V\cdot \text s . A saturated output current density of 603 mA/mm and an ON-resistance of 5.3~\Omega \cdot \text mm was obtained for devices with \textL\text {G}/\textL\text {GS}/\textL\text {GD}/\text{W}\text {G} = 1.5 /1.5/3/ 20~\mu \textm . Meanwhile, the degradation of dynamic ON-resistance is significantly suppressed due to the effective passivation of surface states by the AlN layer grown by plasma-enhanced atomic layer deposition. [ABSTRACT FROM AUTHOR]