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This paper proposes an offline single-stage light-emitting diode (LED) driver based on a novel approach to reduce low-frequency ripple in LED arrays supplied from mains, while assuring high input power factor (PF). The proposal employs a series resonant dc–dc converter integrated into a bridgeless boost power factor correction (PFC) stage. The resonant stage works to reduce the low-frequency ripple transmitted from the output of the PFC stage to the LEDs with only small power losses. This solution achieves three main goals: 1) reduction of the bulk capacitance used at the dc bus, allowing for the use of long-life film capacitors; 2) increase in the overall efficiency of the LED driver owing to the low switching and conduction losses in the shared switching network; and 3) assuring high input PF. Experimental results of a driver without electrolytic capacitors for a 100-W street lighting LED luminaire are presented, showing overall efficiency in excess of 92%, input PF greater than 0.97, and line current harmonic content in compliance with the IEC 61000-3-2 standard. [ABSTRACT FROM AUTHOR]

An open-winding permanent-magnet synchronous generator (PMSG) system with the integration of fully controlled and uncontrolled converter is investigated in this paper, in which half the amount of controllable power switches are needed compared with the conventional open winding system fed by two voltage source converters. The voltage space vector of open winding PMSG is modulated by controlled converter, which will be integrated with the voltage vector by uncontrolled converter to implement the operation of open winding PMSG. In order to analyze and compare the operation capability on the different dc voltage ratios, the available modulation range of the open winding PMSG is analyzed in detail. Moreover, unity power factor control is proposed as the optimized control method to achieve the maximum modulation index. Finally, a 1-kW experimental setup is built to validate the theoretical investigation on the open winding PMSG system. [ABSTRACT FROM AUTHOR]

This paper evaluates the abilities of fast tap-changer topologies by using insulated-gate bipolar transistors to mitigate flicker generated by the ac electric arc furnaces, based on technical and economic criteria. The design problems derived from the very high powers and currents involved have been solved to a preliminary industrial level. The operation of the best resulting topology is verified on a real 80-MVA arc furnace with a dedicated graphical-mathematical multilevel simulator developed to perform short- and long-term tests. Selected pattern windows of the arc voltage, taken from exhaustive logs of electric variables of a real 80-MVA furnace during a complete meltdown process, have been loaded into the simulator. This novel simulation strategy enables the testing of the proposed compensator under reproduced “real working conditions” with several degrees of flicker severity. The simulator includes an IEC flicker meter capable of checking the flicker level online at any point in the installation. The simple open-loop and closed-loop control tests confirm the new tap changer as a fast and economical competitor to other arc furnace compensators. It manages 16% of the furnace system power at a subcycle or supercycle tap changing rate (between 0 and 10 changes per half cycle), as required. This fast switching capacity reduces the compensating time to the very limited values imposed by the L/R time constant of the furnace installation. [ABSTRACT FROM AUTHOR]

This paper presents a new computational approach for solving optimal control problems governed by impulsive switched systems. Such systems consist of multiple subsystems operating in succession, with possible instantaneous state jumps occurring when the system switches from one subsystem to another. The control variables are the subsystem durations and a set of system parameters influencing the state jumps. In contrast with most other papers on the control of impulsive switched systems, we do not require every potential subsystem to be active during the time horizon (it may be optimal to delete certain subsystems, especially when the optimal number of switches is unknown). However, any active subsystem must be active for a minimum non-negligible duration of time. This restriction leads to a disjoint feasible region for the subsystem durations. The problem of choosing the subsystem durations and the system parameters to minimize a given cost function is a non-standard optimal control problem that cannot be solved using conventional techniques. By combining a time-scaling transformation and an exact penalty method, we develop a computational algorithm for solving this problem. We then demonstrate the effectiveness of this algorithm by considering a numerical example on the optimization of shrimp harvesting operations. [ABSTRACT FROM AUTHOR]

A high-efficiency multimode battery charger with an adaptive supply voltage (ASV) control scheme is presented in this paper. The proposed battery charger includes a charging circuit and a dc–dc buck converter. The charging circuit automatically switches among trickle current (TC), constant-current (CC), and constant-voltage (CV) modes corresponding to the battery voltage while the buck converter with ASV control generates an ASV to closely track the battery voltage, leading to significant reduction in the power loss of the charging circuit. To further enhance the efficiency of the battery charger, zero-current detection and nonswitching control schemes are employed to decrease the power consumption of the buck converter in TC and CV modes. The battery charger was implemented with a 0.35- μm CMOS 2P4M process. The experimental results are shown to verify the theoretical analysis of the proposed charger. The maximum efficiency of the overall system is 88.3%, and the maximum efficiency improvement between the proposed charger and the conventional linear charger with fixed supply voltage is up to 11.6%. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

For lack of the appropriate global distribution of dc currents, the conventional suppression method to suppress dc bias based on capacitive dc blocking device (BD) redirects current to the ground as much as possible, which predisposes to the exceeding neutral current of other transformers in the regional power grid and leads to the contradiction between the power grid corporation and other public enterprises. Therefore, this paper presents a flexible suppression method for dc bias based on a novel dc-bias suppression device. First, a current balancing device (CBD) based on adjustable parallel resistances is designed. The mathematical model for global optimal switching of CBDs is established by a field-circuit coupling method with the equivalent resistance network of an ac system along with the location of substations and ground electrodes. The optimal switching scheme to minimize the global maximum dc current is obtained by gravitational search algorithm. Based on the aforementioned work, we propose a suppression strategy considering electro-corrosion of metal pipelines. The effectiveness and superiority of suppression methods are verified by comparative case studies of the Yichang power grid. [ABSTRACT FROM PUBLISHER]

In this paper, a switched reluctance motor (SRM) with phase windings similar to an autotransformer is presented. The new winding structure allows for fast demagnetization. This enhances the machine performance at high speeds. During demagnetization, the dc bus voltage is applied to a portion of the phase winding, and accordingly a higher negative demagnetization voltage/turn is applied. This results in the faster discharge of the phase excitation currents. The power electronic converter configuration is modified to facilitate the new winding topology. However, the number of switches is the same as a conventional half-bridge converter used in SRMs. The proposed SRM drive with the modified winding configuration is verified through finite element analysis based circuit simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents high-isolation single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) substrate integrated waveguide (SIW) mechanical switches in $V$ - and $W$ -bands. Four via holes with the proposed ring-and-cross etching patterns on the top side are placed in the middle of SIW path to block or pass the waves. As the ring-and-cross etching patterns being short-circuited, the via holes block the waves just like stockades do, in other words, turning the switch to OFF mode. And the ring-and-cross etching pattern makes the via holes invisible, turning the switch to ON mode. The $V$ - and $W$ -band SIW SPST and SPDT switches are designed and fabricated. The switches show the measured performances of better than 45-dB isolation for SPST and better than 50-dB isolation for SPDT, for $V$ -band operation, and a better than 50-dB isolation for both SPST and SPDT for $W$ -band operation. [ABSTRACT FROM AUTHOR]

In this paper, two novel hybrid beamforming methods are proposed to reduce the cost and power consumption of hybrid beamformers with a subconnected phase shifter network structure in massive multiple–input multiple–output systems. This is achieved by replacing some of the phase shifters with switches, which, in general, are cheaper and have lower power consumption compared to phase shifters. The proposed methods and the closed-form expressions of their performance are derived according to the properties of the elements of the singular vectors of the channel matrix. In the first approach, it is shown that by combining the subconnected phase shifter network with a fully connected switch architecture, the number of the phase shifters can be reduced up to 50%, while the spectral efficiency is preserved. Then, in order to simplify the structure of the switch network, the fully connected switches are replaced by a subconnected switch network, e.g., binary switches. The analytical and simulation results indicate that just by using 25% of phase shifters, 90% spectral efficiency can be achieved. Finally, simulation results indicate that a similar behavior is observed when the wireless channel is considered to be sparse or correlated. [ABSTRACT FROM AUTHOR]

This paper studies the finite-time stability problem of a class of switched nonlinear systems with state constraints and control constrains. For each subsystem, optimization controller is designed by choosing the appropriate Lyapunov function to stabilize the subsystem in finite time and the estimation of the region of attraction can be prescribed. For the whole switched nonlinear system, a suitable switched law is designed to ensure the following: (1) at the time of the transition, Lyapunov function’s value of the switched-in subsystem being less than the value of the last subsystem; (2) the finite-time stability of the whole close-loop system. Finally, a simulation example is used to verify the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

Considering the existence of many actual influential factors of a high voltage switch cabinet in the coal mine, the paper proposes a hierarchical fuzzy comprehensive evaluation algorithm to assess the running state of the 6 kV (10 kV) power vacuum switch cabinet better and improve operational safety and reliability of the power supply system. The algorithm can realize the state evaluation of bus bars, vacuum circuit breakers, electrical cables, other components, and the switch cabinet by the bottom-up approach. The running state evaluation index system and mathematical model of the switchgear are introduced particularly. According to the different forms of data information, this algorithm comprehensively evaluates the running state of the high voltage switchgear by using the online running data, test data, equipment information, and historical data records of the distribution cabinet. The actual operation states and test data of a handcart switch cabinet are taken as examples to prove the effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

High congestion costs and new congestion patterns, formed by intermittent renewable generation, demand for more efficient utilization of the transmission system. Transmission switching (TS) and variable-impedance series FACTS devices are two technologies that provide such efficiency gains through controlling the power flows. As the system operators begin to utilize these tools, it is essential to understand the interdependence between them at various stages, such as planning and operation. This paper develops an optimal power flow framework that incorporates both FACTS and TS to study the link between the two power flow control technologies. The simulation results on an RTS 96-bus system suggest that: 1) substantial economic savings can be achieved through utilization of both TS and FACTS, beyond the independent capabilities of each technology; 2) performing TS actions affect the optimal location and set point of FACTS devices; and 3) operation of FACTS devices affect the location and frequency of TS actions. It is, thus, essential to acknowledge the interdependence between the two technologies both at the planning and operation stage. Failure to do so will lead to economic inefficiencies that can be avoided through co-optimization of generation dispatch, TS, and FACTS. [ABSTRACT FROM PUBLISHER]

This paper considers line switching as a remedial action to mitigate the geomagnetically induced currents (GICs) in large-scale power syste-kazerooni-2753840ms. The algorithm uses linear sensitivity analysis to find the best switching strategy which minimizes the GIC-saturated reactive power loss. Furthermore, the coupling between the ac power flow solution and the GIC flows is modeled and heuristic strategies are designed to maintain the system security measures in terms of both GICs and ac power flow. Finally, the computational complexity of the algorithm is analyzed for large-system implementations. To reduce the complexity, the critical lines are identified through the sensitivity analysis and the calculations are performed only on the reduced system. The effectiveness of the proposed algorithm is demonstrated through numerical results using a small 20-bus test case as well as large power systems. [ABSTRACT FROM PUBLISHER]

This paper presents a single-stage light-emitting diode (LED) driver based on a bridgeless power factor correction (PFC) converter and a half-bridge CLCL resonant converter for street lighting applications. The proposed single-stage topology integrates the PFC converter and the CLCL resonant converter by sharing active power switches. The bridgeless PFC converter adopts two buck–boost circuits operating in discontinuous-conduction mode to achieve input-current shaping. It uses two diodes instead of a rectifier bridge to reduce the power loss caused by the diodes. Owing to its superior soft-switching characteristics, the CLCL resonant converter is used. The proposed LED driver has superior features, such as high efficiency, near unity power factor, low total harmonic distortion, and relatively few diodes. A 100-W lab prototype is successfully implemented, and the experimental results verify the effectiveness and feasibility of the proposed LED driver. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase multilevel ac/ac converter with reduced number of power semiconductor devices is proposed. For the simple case of a three-level converter, only three bidirectional switches and two capacitors are required. The proposed converter provides a highly sinusoidal and regulated output voltage with a simple topology. The efficiency is high because in each state of operation only one semiconductor conducts. The converter can be easily extended to any desired levels in the output voltage to even more reduce the output total harmonics distortion. Another advantage of the proposed converter is that by increasing the voltage levels, the stress on the switches will decrease. The proper performance of the proposed converter is confirmed through extensive simulation and experimental tests. [ABSTRACT FROM PUBLISHER]

Increasing the resonant frequency of a wireless power transfer (WPT) system effectively improves the power transfer efficiency between the transmit and the receive coils but significantly limits the power transfer capacity with the same coils. Therefore, this paper proposes a coil design method for a series-series (SS) compensated WPT system which can power up the same load with the same DC input voltage & current but with increased resonant frequency. For WPT systems with higher resonant frequencies, a new method of realizing soft-switching by tuning driving frequency is proposed which does not need to change any hardware in the WPT system and can effectively reduce switching losses generated in the inverter. Eighty-five kHz, 200 kHz and 500 kHz WPT systems are built up to validate the proposed methods. Experimental results show that all these three WPT systems can deliver around 3.3 kW power to the same load (15 W) with 200 V input voltage and 20 A input current as expected and achieve more than 85% coil-system efficiency and 79% system overall efficiency. With the soft-switching technique, inverter efficiency can be improved from 81.91% to 98.60% in the 500 kHz WPT system. [ABSTRACT FROM AUTHOR]

This paper proposes a technique for switch current stress reduction in a Switched Inductor DC‐DC Boost Converter (SIBC). The proposed technique comes up with a low‐cost design, high voltage conversion ratio with a less duty cycle value, and lower current stress without increasing the component count. This topology is basically a transformer‐less design where one diode of the traditional switched inductor configuration has been replaced with a switch, which is in parallel with the existing switch, resulting in a design that can incorporate active switches with a low current rating, since the total input current is equally shared by them. The detailed modes of operation in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) and steady‐state analysis, the non‐idealities' effect on voltage gain, design approach, and a comparative study with other DC‐DC converters for some significant performance characteristics are provided. The experimental validations for the performance and working of the 500 W designed prototype are presented. [ABSTRACT FROM AUTHOR]

This paper presents two hybrid six-phase machine drive systems. The topologies are considered to be hybrid because two three-phase groups of the machine are fed by different types of converters. The purpose of these topologies is to be alternative configurations, being midway between the conventional six-leg two-level (2L) inverter, composed of 12 switches, and more complex structures, such as the six-leg three-level neutral point clamped (3L-NPC) inverter, composed of 24 switches and 12 clamping diodes, or the conventional 12-leg dual inverter, composed of 24 switches. One of the hybrid topologies is composed of 18 switches and the other is composed of 18 switches and 6 clamping diodes. A comparative study of harmonic distortion, semiconductor losses, and machine torque ripple is performed. Compared with the conventional 2L inverter, the proposed systems provide better performance in terms of harmonic distortion, overall semiconductor losses, and machine torque ripple and are less complex than dual and NPC inverters. Pulse width modulation (PWM) strategy is discussed and simulated. A modification in PWM strategy of the hybrid configurations is performed in order to obtain similar torque ripple to the cases when dual and 3L-NPC converters are used, even with lower number of semiconductor devices. Experimental results are also presented in order to validate the PWM strategy. [ABSTRACT FROM AUTHOR]

This paper presents design criteria for four-terminal phase-change (PC) RF switches as a function of their dimensions, (heater width, RF gap, and barrier thickness), materials, and connection topology. Reducing heater width is shown to reduce switch actuation power, with this reduction ultimately being limited by the maximum allowed heater current density, as set by projected reliability. Narrower RF gaps are shown to increase switch cut-off frequency F\mathrm {CO} , because they decrease on-state resistance more than they increase off-state capacitance. The balance of this increased F\mathrm {CO} versus the estimated reduction in power handling as the RF gap shrinks is quantified. Barrier layers of AlN thicker than 200 nm are shown to be sufficient to electrically decouple the switch from the heater trace. Coupling to heater pads can also be significant unless pad sizes are reduced as in a monolithically integrated switch. Finally, it is demonstrated that division of the switch into multiple parallel segments is a viable approach for lowering the heater actuation voltage for CMOS integration. A 12.5% increase in C\mathrm{\scriptscriptstyle OFF} (~1.5 fF) was observed and 35% increase in actuation power at temperature was needed in a two-segment parallel switch, as compared to a single segment switch. [ABSTRACT FROM PUBLISHER]

Linear flux-switching permanent magnetic (LFSPM) machines are good choices for long stroke applications. These machines deliver high thrust force density in addition to the machine structure where permanent magnetics (PMs) and windings are all on the short mover. For LFSPM machines, their performance is always affected by big thrust force ripple. In this paper, for two C-core LFSPM machines of high thrust force capability, including a 6/13 C-core LFSPM (6/13LFSPM-C) machine and a sandwiched C-core LFSPM (SLFSPM-C) machine, and a thrust force ripple reduction method is proposed. The proposed method is developed by reducing the slot effect component of the cogging force based on staggered stator tooth, and suppressing the thrust force ripple caused by unbalanced three phase back-electromagnetic forces (EMFs) based on two end PMs. Based on finite element analysis (FEA) results, both C-core LFSPM machines can achieve small thrust force ripples as well as high sinusoidal back-EMFs, and at the same time, maintain high thrust force capability with the proposed method. It was also found that, the improved SLFSPM-C machine exhibited the same thrust force capability as the improved 6/13LFSPM-C machine, but with a much smaller thrust force ripple. [ABSTRACT FROM AUTHOR]

A high-speed earthing switch (HSES) of a gas-insulated switchgear (GIS) performs a secondary role in protecting the power system in the event of an accident. After being interrupted by a circuit breaker (CB), the short-circuit current remaining in the network should be earthed by the HSES. However, as the contacts of the HSES may have been damaged by a pre-arc during the closing operation, the HSES may fail to ground the short-circuit current. To successfully ground the short-circuit current, the contacts of the HSES must be protected from damage by the pre-arc. Thus, minimizing the pre-arcing time is required to step up the making performance. This paper analyzes the making performance of the HSES by predicting the pre-arcing time within the short-circuit current making test. To estimate the pre-arcing time, we compared the results of analytical calculations based on streamer discharge theory and the numerical simulations of the electric field strength. By conducting a short-circuit current making test for a 420 kV 63 kA HSES in a high-power laboratory, the pre-arcing time calculation results were verified. A comparison of the results showed that the proposed prediction method was useful for verifying the performance of the HSES. [ABSTRACT FROM AUTHOR]

In this paper, analytical expressions for waveforms and design relationships are derived for the class-E power amplifier with the MOSFET nonlinear drain-to-source parasitic capacitance under the subnominal operation, i.e., only zero-voltage switching (ZVS) condition, for any grading coefficient m of the MOSFET body junction diode and 50% duty ratio. Only the MOSFET nonlinear drain-to-source parasitic capacitance is used for the analysis of the class-E ZVS power amplifier, and its nonlinearity is determined by the grading coefficient m. The switch voltage waveform does not satisfy the class-E ZVS switching condition when only the linear shunt capacitance is considered. The grading coefficient m is used as an adjustment parameter that provides accurate design to satisfy the given output power and peak switch voltage simultaneously. Therefore, the grading coefficient m is the important parameter to satisfy the class-E ZVS condition and given design specifications, which is the most important result in this paper. Additionally, the output power capability and maximum operating frequency are affected by the grading coefficient m. The analytical expressions are obtained by considering the grading coefficient m as an adjustment parameter, which is validated by PSpice simulations and laboratory experiments. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which denotes the usefulness and effectiveness of our obtained analytical expressions. [ABSTRACT FROM AUTHOR]

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of >\0 dBm, while consuming 48 mA from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

This paper proposes a boost driver with an improved charge-pump (CP) circuit. The CP circuit includes electric double-layer capacitors (EDLCs) that can keep their voltages at a constant level during motor acceleration and deceleration. By changing the connection between the EDLCs and a supply source with electrical switches in the CP circuit, the driver can adjust its dc link voltage to three voltage levels. The voltage regulator of the driver uses a space-vector modulation (SVM) technique. Space-vector diagrams to adjust the dc link voltage in the driver are proposed. The driver operated in the SVM technique using the proposed diagrams can reduce the harmonics in the output and charge the EDLCs during motor drive operation. Experiments confirm that the driver can control the motor with the same performance level as the conventional boost driver and can maintain its performance level continuously. [ABSTRACT FROM PUBLISHER]

A comprehensive method of electromagnetic emission interference (EMI) reduction in dc/ac inverters through periodic dithering of the pulse-width modulated (PWM) switching frequency is presented in this paper. The periodic dithering is the process of changing the switching frequency of the PWM signal that drives the switches of the power electronics inverter. The effects of the various parameters involved in the PWM dithering process have been analyzed in this paper. The important parameters involved in the dithering process are the frequency range used for dithering, the periodic time of the dithering signal, and the phase of the dithering signal. The effect of each of these parameters has been studied to determine their values that minimize the EMI. Additionally, analytical expressions for theoretical prediction of the EMI levels at different frequencies have been derived for performance analysis during the design stage. The theoretical predictions for the dithering signals have been found to accurately correlate with both the simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase dc/ac converter topology with soft-switching operation. The proposed converter achieves soft-switching by using DCM (discontinuous current mode) operation and a common turn-off snubber capacitor connected to the dc terminals of a full-bridge configuration. One additional semiconductor switch is used to disconnect the snubber capacitor from the dc side, and allows the snubber capacitor to be discharged. The DCM operation realizes zero-current turn-on and the snubber capacitor achieves zero-voltage turn-off. The proposed converter can be applied to a grid-connected converter for domestic renewable energy and energy storage, including Photovoltaic and battery energy storage devices. This paper describes operation principles, control and modulation techniques as a grid-connecting converter. Experimental verification including loss analysis with a 1-kW pilot device is provided. [ABSTRACT FROM AUTHOR]

Nowadays, electronics face a challenge regarding the power consumption of integrated circuits (ICs). There is a need for new devices that can provide improved switching capabilities. The downscaled electrostatically actuated ohmic switch, as a (re)emerging device, is a promising candidate to meet this need. To bring such a device seamlessly into IC design, it must be accompanied by an accurate, fast and robust analytical compact model. The development and the main characteristics of such a model are described within this paper. Extensive numerical simulations and measurements have been used to validate the model. [ABSTRACT FROM AUTHOR]

This paper illustrates the development and the experimental validation of a life model for light emitting diodes (LEDs) able to predict the time to failure under different stress conditions associated with the value and time dependence of applied forward current. In the paper, three different life models are derived by exploiting the results of tests under constant forward current. Then, experiments performed by subjecting LEDs to simple load cycles characterized by step-varying forward current are carried out, and the results are employed as a benchmark for the predictions provided by the combined use of the life models derived under constant stress and cumulative damage theory. [ABSTRACT FROM AUTHOR]

The single-chip crosspoint-queued (CQ) switch is a compact switching architecture that has all its buffers placed at the crosspoints of input and output lines. Scheduling is also performed inside the switching core and does not rely on latency-limited communications with input or output line-cards. Compared with other legacy switching architectures, the CQ switch has the advantages of high throughput, minimal delay, low scheduling complexity, and no speedup requirement. However, the crosspoint buffers are small and segregated; thus, how to efficiently use the buffers and avoid packet drops remains a major problem that needs to be addressed. In this paper, we consider load balancing, deflection routing, and buffer pooling for efficient buffer sharing in the CQ switch. We also design scheduling algorithms to maintain the correct packet order even while employing multi-path switching and resolve contentions caused by multiplexing. All these techniques require modest hardware modifications and memory speedup in the switching core but can greatly boost the buffer utilizations by up to 10 times and reduce the packet drop rates by one to three orders of magnitude. Extensive simulations and analyses have been done to demonstrate the advantages of the proposed buffering and scheduling techniques. By pushing the on-chip memory to the limit of current ASIC technology, we show that a cell drop rate of 10^-8, which is low enough for practical uses, can be achieved under real Internet traffic traces corresponding to a load of 0.9. [ABSTRACT FROM AUTHOR]

This paper proposes a real-time hybrid fuzzy bang–bang (BB) controller with switching function, in order to implement a full nonlinear control law. The controller consists of a fuzzy-BB controller in parallel with a BB controller while the system is in operation. In order to circumvent the shortcomings of fuzzy-BB and BB-based controllers, a hybrid fuzzy-BB controller is proposed, in which the output can be either the outputs of the two, i.e., the fuzzy-BB or BB units that are being switched as per the absolute error signal. Normally, the BB controller operates in general; the fuzzy-BB controller is activated when the drive system experiences oscillatory behavior. The choice between the fuzzy-BB and BB controllers is based on a set of simple if–then rules; the overshoot and the oscillatory behavior have to be detected by the absolute errors. Trajectory tracking of nonlinear motor drives in position mode serves as a test bed for the control law, and a real-time experiment allows for the assessment of its practical applicability. The hybrid fuzzy-BB controller has been implemented on hardware with a dSPACE digital signal processor, and it is observed that the performance of the controlled brushless dc motor drive with the hybrid fuzzy-BB controller is assuring. Noticeably, experimental results demonstrate that the proposed controller is capable of significantly cultivating the motor performance under random disturbance and different loading conditions. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

This paper investigates a new family of converters for high-power transfer between dc buses with different voltage levels. The proposed converters achieve high-voltage dc-dc conversion without an intermediate ac conversion stage. Three converter circuits are investigated, all based on the use of a common switching cell module. The first is a step-down converter, the second is a step-up converter, and the third is an inverting step-up/downconverter. For each converter, the structure is presented, its operation principle is explained, and the design equations are derived. A comparative analysis between the converters is carried out to highlight the merits and limitations of each topology. [ABSTRACT FROM PUBLISHER]

The measurement of partial discharge (PD) using ultra-high frequency (UHF) method is considered an effective approach to monitor the online condition of the equipment, which is used to facilitate the detection of incipient defects in gas-insulated switchgear (GIS). In this paper, in order to assess the severity of PD defects using UHF method, the actual 220-kV GIS were subjected to experimentation. The PD was measured simultaneously by using the UHF method and the IEC60270 measurement technique. The combined measurement has been carried out on different defects in PD test cells, including the floating metal, metallic protrusion, and void in epoxy resin. The inner coupler installed in the GIS tank, and the outer coupler placed outside the spacer, are used to measure the UHF signal. The relationship of the apparent charge and the amplitude of the time-domain signal, and the integral energy from 300 MHz to 1.6 GHz of the signal induced by PD in GIS are analyzed thoroughly. In this way, the severity of PD can be quantified using the UHF signal. In addition, to verify the sensitivity of the UHF detection method, a pulse generator with a rise time of about 500 ps is designed. The GIGRE method for the verification of sensitivity, which is used worldwide, is applied in the experiment. The results of the pulse generator experiment are compared to the results produced by the actual discharge sources, and several possible approaches of improving this method are proposed. [ABSTRACT FROM PUBLISHER]

This paper describes phase current reconstruction methods from dc-link currents in three-phase three-level PWM inverters. Since the three-level inverters have three paths between dc-link and power switches, the reconstructions differ from that in two-level inverters which have two paths there. Considering these paths in three-level inverter, this paper proposes the methods for phase current reconstruction. While the reconstruction method is executed by the currents sampled on the dc-links, the system encounters current-unmeasurable areas where the dc currents cannot be sampled due to the lack of measurement time according to the PWM status. This paper analyzes the areas and proposes a minimum voltage injection method for minimizing them to guarantee accurate current reconstruction. The method provides the expanded operating areas especially in low-output voltage operation and the minimized distortions in output voltages. The feasibility of the proposed method has been assessed in experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a new bidirectional dc–dc converter capable of improving the convenience and modularity of the dc power grid system. By the unique operation of the $LC$ resonant transformer, the proposed converter achieves bidirectional power control with only two switches. Also, the resonant transformer drives the soft switching turn-on and turn-off over a wide power range. Hence, the circuit has high potential to downsize the converter by exploiting high frequency and simplicity. This paper provides the operating principle and the experimental verification of the proposed circuit. A prototype was fabricated by using a simple and high-density printed circuit board ($\geq$ 10 W/cc). It is verified that the circuit resonant operation successfully drives bidirectional power control with high efficiency ($\geq$ 92%). An application example is also provided for dc grid system integration. [ABSTRACT FROM PUBLISHER]

Generally, for pulsed power applications with low jitter and high repetition rates, the use of semiconductor switches have replaced the traditional gap switches and thyratron circuits due to the limited lifetime of the thyratron and gap switches under such operating conditions. However, the limited ratings of these semiconductor switches require series and/or parallel stacking in order to handle high voltages and current levels associated with the discharge energy. Described in this paper is the design of a high voltage switch that uses a simple and reliable gate driver circuit for pulsed power application. In this design, the switch module is made up of insulated-gate bipolar transistor (IGBTs) and their gate driver circuits compactly fitted onto a single module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier synchronization of the switches, the simultaneous transfer of both signal and power for current boost are also described in this paper. A 120 nF capacitor bank energy was discharged using a configuration of the developed high voltage switch and a developed 15 kV, 1.5 kJ/s peak power capacitor charger, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging. [ABSTRACT FROM AUTHOR]

Insulation monitoring is crucial to personal safety and equipment operation in the power distribution system. Recently, with the rapid development of distributed generators, the three-phase voltage-source PWM converter (VSC) is widely used as the bidirectional interface between the dc microgrids and the distribution networks. This paper presents the relationship between the response of insulation monitoring device (IMD) and the neutral-point voltage deviation (NPVD) of VSC, by analyzing the disturbances of the switching function and the dc-side insulation balancing. Then, a method of detecting the NPVD for grid-connected VSC is proposed, based on the dc signal injection and the Duffing oscillator. Furthermore, the proposed method takes the mean and spectrum of the neutral-point voltage as the primal characteristics. Thus, the dc signal injection is adopted to detect the mean of the neutral-point voltage, and the Duffing oscillator is adopted to determine the frequency disturbance of the neutral-point voltage, respectively. The test result confirms the existence of the neutral-point voltage deviation and verifies the availability of the proposed method. Hence, the proposed method could be used to improve the response of IMD. [ABSTRACT FROM AUTHOR]

Preinsertion resistors (PIR) are used in combination with circuit breakers to absorb switching transients and come into effect during the “closing” operation of the breaker. It is mainly used for rated voltages equal to or higher than 420 kV for line lengths above 200 km. Although it is an important component, power testing of complete PIR is very complicated and not well defined. Therefore, an attempt has been made in this paper to provide alternative test methods for power testing of PIR without compromising its important parameters. Due to high energy requirements and limitations of the test laboratory, a multipart testing of PIR is necessary to prove its thermal capability and dielectric behavior. Before proceeding with the complete PIR test, the critical parameters of PIR, such as mechanical insertion time, rate of decay of dielectric strength of the interrupter, and PIR switch, etc., should be verified with testing. These test procedures are also explained in detail along with a method to theoretically evaluate electrical insertion time for different network conditions. The series PIR configuration for the metal-enclosed \mathrmSF6 system has been considered in this paper. [ABSTRACT FROM AUTHOR]

A novel readout circuit for interfacing single element resistive sensors is presented in this paper. The proposed scheme is based on a new relaxation oscillator (RO). The RO, along with a timer counter provides a digital output proportional to the resistance of the sensor. The output characteristic of most of the existing readout circuits for resistive sensors suffers from gain, offset, and nonlinearity errors. The sources of errors include various nonideal circuit parameters and their drift. The output of the proposed readout circuit has a special feature that it is not a function of the circuit parameters such as: 1) offset voltages of the opamps and comparators; 2) bias currents of the opamps and comparators; 3) gain of various units employed; 4) ON-resistance of the switches; 5) value or mismatch in the magnitudes of the reference voltages employed; 6) delay of the switches and comparator; 7) leakage current of the switch; and 8) slew rate of the opamp. Such a scheme will be useful for high accuracy measurements, even when the parameters 1)–8) may vary or drift, due to variation in the measurement environment. A prototype of the proposed readout scheme has been developed in the laboratory and the performance has been evaluated under various conditions. The output was found to be linear with a worst-case nonlinearity of 0.05%. Test results from a prototype developed show that the proposed scheme possesses all the features, described above, as expected. [ABSTRACT FROM PUBLISHER]

This part of the paper takes a new look at the stability of the fundamental periodic behavior and the associated subharmonic oscillation boundary in dc–dc switching regulators with fixed-frequency pulse width modulation. After revisiting different approaches applied to a unified reduced-order model of switching regulators, the work presents a novel way of obtaining such a boundary without any simplification nor order reduction. A new simple closed-form condition is then obtained using the new approach, which is valid for different strategies with both trailing edge and leading edge modulation schemes. The critical condition is obtained from the steady-state response using an asymptotic approach without resorting to frequency-domain Fourier analysis or using the monodromy or the Jacobian matrix of the discrete-time model. Unlike the method based on the Fourier series expansion, the proposed method does not require the use of any transform and, most importantly, can be applied to bilinear switching regulators. As a byproduct of the proposed method, a singularity problem that is encountered in steady state, when the system involves integrators in the feedback loop, is addressed and a solution is developed to achieve a closed-form expression in the presence of such integrating feedback loops. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

This paper extends the voltage-doubler concept to the single-phase SEPIC rectifier in discontinuous conduction mode and, as a consequence, novel rectifiers are proposed. A comparison with the classic SEPIC rectifier shows that the proposed converters can either provide reduced voltage stress on the semiconductors for the same output voltage level or supply double the gain of the output voltage with the same voltage stress. The proposed voltage-doubler SEPIC rectifiers provide a high power factor with no current control and they can be applied in order to improve the static gain of the structure, which can make the SEPIC rectifier suitable for applications that require a high voltage level. In this paper, the generic structure based on a three-state switch, four different implementations of the proposed concept (including bridgeless structures), steady-state analysis, a dynamic model, system control, and experimental results are presented. The proposed rectifiers were verified by experimental results obtained with a prototype built with the following specifications: 1000 W output power, 220 V input voltage, 400 V output voltage, and 50 kHz switching frequency. Peak efficiency of 95.84%, THD of 2%, and power factor of 0.9997 were obtained and, most importantly, double the gain of the output voltage was verified. [ABSTRACT FROM AUTHOR]

This paper presents a single-inductor multiple-output (SIMO) LED driver with precise dimming and full dimming range. Based on the coordination of a string-level scheme and a system-level dimming scheme, the proposed SIMO LED driver can overcome practical constraints of existing SIMO LED drivers such as limited dimming range and needs for high-current switches. The proposal can achieve dimming precision up to an accuracy of 0.8% and also full dimming range. It has the flexibility of using either phase-shift or synchronous pulsewidth-modulated (PWM) switching for dimming control. The proposed circuit and control operations have been practically verified with a 25-W off-line SIMO-driven LED system. Practical evaluations of its power quality and energy efficiency are also provided. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a multilevel ac six-phase motor drive. The system is composed of five isolated three-leg voltage source inverters feeding the open-end windings of an asymmetrical six-phase induction motor (SPIM), which is adequate to generate multilevel voltages for high-power systems with voltage rating restrictions. A simple space vector pulse-width modulation (PWM) based on three similar individual planes and its implementation by means of equivalent level-shifted PWM are presented. A space vector pattern with a high number of voltage vectors redundancies is obtained. These redundancies and the application sequence of the voltage vectors are selected to minimize the amount of changes in the switching states and to decrease the harmonic distortion of the generated voltages. The vector pattern of this optimal modulation is obtained by analyzing only one plane and applied in the same way to the three planes as if they were independent. The developed PWM techniques have low computational complexity and are suitable for low-cost hardware implementations. Simulation results are used to compare the proposed topology with a conventional configuration in terms of harmonic distortion and semiconductor losses. Experimental results demonstrate the feasibility of the proposed drive system. [ABSTRACT FROM AUTHOR]

Usually, the high-gain high-efficiency dc–dc converters consist of many passive components, which increases the order of the system. As the order increases, system modeling and control become more complex. Thus, there is a need for the simplification of the small signal modeling process of such converters. This paper presents a generalized small signal model and equivalent circuit for an $n$ th-order coupled-inductor-based high-voltage gain converters (CIHVGC) that can be conveniently used for the control design. The state variable representation of a generalized coupled inductor with p windings is included. A simplified step by step procedure to obtain small signal model using visual inspection is presented. Analysis is included and verified using simulations and experiments for the output voltage regulation of high-voltage gain converters. The usefulness and versatility of the proposed model is verified with three examples of high gain converters belonging to the CIHVGC family. All the analytical, simulation, and experimental details of this paper are presented. [ABSTRACT FROM AUTHOR]