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Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

Background: Microfluidic chip detection technology is considered a potent tool for many bioanalytic applications. Rapid detection of foodborne pathogens in the early stages is imperative to prevent the outbreak of foodborne diseases, known as a severe threat to human health. Conventional bacterial culture methods for detecting foodborne pathogens are time-consuming, laborious, and lacking in pathogen diagnosis. To overcome this problem, we have created an embedded paper-based microchip based on isothermal loop amplification (LAMP), which can rapidly and sensitively detect foodborne pathogens. Results: We embed paper impregnated with LAMP reagent and specific primers in multiple reaction chambers of the microchip. The solution containing the target pathogen was injected into the center chamber and uniformly distributed into the reaction chamber by centrifugal force. The purified DNA of Escherichia coli O157:H7, Salmonella spp., Staphylococcus aureus, and Vibrio parahaemolyticus has been successfully amplified and directly detected on the microchip. The E. coli O157:H7 DNA was identified as low as 0.0134 ng μL− 1. Besides, the potential of this microchip in point-of-care testing was further tested by combining the on-chip sample purification module and using milk spiked with Salmonella spp.. The pyrolyzed milk sample was filtered through a polydopamine-coated paper embedded in the inside of the sample chamber. It was transported to the reaction chamber by centrifugal force for LAMP amplification. Then direct chip detection was performed in the reaction chamber embedded with calcein-soaked paper. The detection limit of Salmonella spp. in the sample measured by the microchip was approximately 12 CFU mL− 1. Conclusion: The paper embedded LAMP microchip offers inexpensive, user-friendly, and highly selective pathogen detection capabilities. It is expected to have great potential as a quick, efficient, and cost-effective solution for future foodborne pathogen detection. [ABSTRACT FROM AUTHOR]

[Display omitted] • A method for fabricating integrated multi-electrodes inside a single sheet of paper. • A paper used in two dimensions used as a three-dimensional scaffold. • The control of the equivalent circuit without changing external circuits and wires. Paper is an excellent substrate for flexible devices due to its various advantages such as flexibility, porosity, lightness, and thinness. Its inherent characteristics can be also exploited to overcome the limitations of conventional substrates, such as weak adhesion and large mass densities. Here, we propose a method for fabricating vertically integrated multi-electrodes within only a single sheet of paper. Despite the randomly distributed fibrous networks in a paper, the multi-layered electrodes were uniformly formed and completely separated by applying a removable hydrophobic wax barrier confinement inside a single sheet of paper. The integrated multi-layer electrodes inside a single sheet of paper mean that conventional two-dimensional planes can be used as three-dimensional scaffolds. The highly integrated electrodes and circuit systems are located within only a sheet of paper, making a new possibility to design maximizing the energy storage performance, integrated circuit systems, and significantly decreasing the thickness of the system without external complex structure. In consequence, this unique platform can circumvent most of the fabrication challenges related to two-dimensional energy storage sheets. [ABSTRACT FROM AUTHOR]

All-inkjet-printing of transistors has received much attention for low cost and flexible integrated circuits. However, most flexible field-effect transistors (FETs) based on the emerging two-dimensional materials suffer from the high cost of substrate and electrode materials. The requirements for high-temperature synthesis and precise control in processing add another layer of complexity. To overcome these issues, low-cost flexible paper-based MoS2 FETs were fabricated by inkjet printing of MoS2 channel materials on paper. Additionally, we proposed and achieved the mask-less and low-temperature formation of source and drain electrodes on paper using in-situ selective-area copper reduction. A low sub-threshold swing of 80 mV/dec, high on/off ratio of 105, and very high turn-on current (Ion) of 200 μA of the paper-based flexible MoS2 FETs were demonstrated using the proposed low-cost and facile all-inkjet-printing technique. The all-inkjet-printing technique assisted by in-situ copper reduction opens new opportunities for low-cost and batch fabrication of paper-based electronic devices in ambient conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

A rule-based expert system for the integrated control and supervision of the dry-end sections of a paper machine is proposed. This. system is capable of recognizing all the normal and abnormal changes in process operating conditions, including acceleration of sections, threading of paper sheet, nip pressure activation, activation and deactivation of tension control loops, change of parent roll, and sheet break. A core part of the system is the supervision of the sensorless tension control of the dry-end sections, assuring its long-term stability. [ABSTRACT FROM AUTHOR]

Traditional diagnostic tests for chronic diseases are expensive and require a specialized laboratory, therefore limiting their use for point-of-care (PoC) testing. To address this gap, we developed a method for rapid and low-cost C-reactive protein (CRP) detection from blood by integrating a paper-based microfluidic immunoassay with a smartphone (CRP-Chip). We chose CRP for this initial development because it is a strong biomarker of prognosis in chronic heart and kidney disease. The microfluidic immunoassay is realized by lateral flow and gold nanoparticle-based colorimetric detection of the target protein. The test image signal is acquired and analyzed using a commercial smartphone with an attached microlens and a 3D-printed chip-phone interface. The CRP-Chip was validated for detecting CRP in blood samples from chronic kidney disease patients and healthy subjects. The linear detection range of the CRP-Chip is up to 2 µg/mL and the detection limit is 54 ng/mL. The CRP-Chip test result yields high reproducibility and is consistent with the standard ELISA kit. A single CRP-Chip can perform the test in triplicate on a single chip within 15 min for less than 50 US cents of material cost. This CRP-Chip with attractive features of low-cost, fast test speed, and integrated easy operation with smartphones has the potential to enable future clinical PoC chronic disease diagnosis and risk stratification by parallel measurements of a panel of protein biomarkers. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

This special issue contains papers obtained through open call-for-papers as well as from the selected extended versions of the papers presented in the 4th International Conference "2021 Devices for Integrated Circuit (DevIC)", held at Kalyani Government Engineering College from May 19-20, 2021. This special issue publishes a collection of papers that were submitted to the Journal of Materials Science: Materials in Electronics on the theme of experimental electronic and optical materials for nano-dimensional device applications. [Extracted from the article]

The author presents a history of his efforts to design sustainable and economical circuit construction on paper, which he finds more akin to craft than industry. He focuses on a collection of modules called Rollz-5, which creates organic rhythms out of geometrical forms. A future application of this work will be to create radio devices based on the Platonic solids. [ABSTRACT FROM AUTHOR]

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]

This paper deals with a low-cost method for the assembly of flexible substrate antennas and UHF RF identification silicon (Si) chips. Such a method exploits a magnetic coupling mechanism, thus not requiring for galvanic contacts between the Si chip and antenna itself. The magnetic coupling is established by a planar transformer, the primary and secondary windings of which are implemented on flexible substrate and Si chip, respectively. As a result, the Si chip can be assembled on the antenna with a mere placing and gluing process. First, the idea has been validated by theory. Electromagnetic simulations of a square heterogeneous transformer (1.0-mm side) show a maximum available power gain (MAG) of -0.4 dB at 868 MHz. In addition, the heterogeneous transformer is also quite tolerant with respect to misalignment between primary and secondary. An offset error of 150 \mu\ m reduces the MAG to -0.5 dB. A sub-optimal matching strategy, exploiting a simple on-chip capacitor, is then developed for antennas with 50-\Omega input impedances. Finally, the idea has been experimentally validated exploiting printed circuit board (PCB) prototypes. A PCB transformer (1.5-mm side) and a transformer rectifier (two-diode Dickson multiplier) have been fabricated and tested. Measurements indicates a MAG of -0.3 dB at 868 MHz for the transformer and the capability of the developed rectifier to supply a 220-\k\Omega load at 1.5 V with a -2-dBm input power. [ABSTRACT FROM AUTHOR]

Origami, an ancient form of papercraft, provides a way to develop functional structures for engineering applications. In this paper, we report an approach to design and manufacture a stretchable circuit board (SCB) with origami structures. The benefits of developable, flat-foldable, and rigid-foldable origami-based structures as SCBs are discussed, and a representative structure, Miura fold (or Miura-ori), is chosen to be investigated. Under the constraints induced by the mounted components' dimensions, the Miura-ori structures for specific applications can be defined. We propose three methods for better fabrication, including direct folding, stiffness modification, and kirigami enhancement, to improve a planar sheet's foldability. A wearable ECG (electrocardiogram) system based on MO-SCB (Miura-ori enabled SCB) technology is built, and the stretchable portion is made of commercial FPCBs (flexible printed circuit board), providing desired stretchability and reliability. The proposed technology routine is compatible with industrial production and may pave the application of stretchable electronics. [ABSTRACT FROM AUTHOR]

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]

Although Moore's Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)..., longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor. [ABSTRACT FROM AUTHOR]

Tetracycline is widely used as medicine for disease treatments and additives in animal feeding. Unfortunately, the abuse of tetracycline inevitably causes tetracycline residue in animal-origin foods. Though classical methods can detect tetracycline in high sensitivity and precision, they often rely on huge and expensive setups as well as complicated and time-consuming operations, limiting their applications in rapid and on-site detection. Here, we propose a handheld inkjet printing paper chip based smart tetracycline detector: tetracycline can be determined by inkjet printing prepared paper chip based enzyme-linked immunosorbent assay (ELISA) with the advantages of high sensitivity, excellent specificity and low cost; moreover, a smartphone based paper chip reader and application is designed for automatically determining tetracycline with simple operations, high precision and fast speed. The smart tetracycline detector with a compact size of 154 mm × 80 mm × 50 mm and self-supplied internal power can reach a rather low detection limit of ~0.05 ng/mL, as proved by practical measurements. It is believed the proposed handheld inkjet printing paper chip based smart tetracycline detector is a potential tool in antibiotic sensing for routine uses at home and on-site detection in the field. [ABSTRACT FROM AUTHOR]

The article offers information on use of inkjet-printed paper-based Radio Frequency Identification (RFID) circuit device for Ultra high frequency (UHF) and microwave antenna applications. Topics discussed include benefit of low-cost applications; information on the fabrication of paper-based RFID tag using a non-planar ramp to connect the inkjet-printed electronic and an unpackaged silicon integrated circuit (IC); and views on the reliability inkjet-printed paper-based RFID tag .

We propose a technique for the wafer-level testing of the gate dielectrics of metal–insulator–semiconductor (MIS) devices by the high-field injection of electrons into the dielectric using a mode of increasing injection current density up to a set level. This method provides the capability to control a change in the charge state of the gate dielectric during all the testing. The proposed technique makes it possible to assess the integrity of the thin dielectric and at the same time to control the charge effects of its degradation. The method in particular can be used for manufacturing processes to control integrated circuits (ICs) based on MIS structures. In the paper, we propose an advanced algorithm of the Bounded J-Ramp testing of the gate dielectric and receive its approval when monitoring the quality of the gate dielectrics of production-manufactured MIS devices. We found that the maximum value of positive charge obtained when tested by the proposed method was a value close to that obtained when the charge was injected into the dielectric under a constant current with a Bounded J value despite large differences in the rate of degradation of the dielectric. [ABSTRACT FROM AUTHOR]

This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied. [ABSTRACT FROM AUTHOR]

This paper proposes the high speed low power analysis of 12 transistors 2x4 Low Power (LP) and Low Power Inverting (LPI) Decoders by using Dual Value Logic (DVL) and Complementary Metal Oxide Semiconductor (CMOS) Logic. A huge challenge faced by this era of developing is power reduction. The LP circuit design is a requesting issue in high performance digital frameworks, for example, microchips, DSPs and other different applications. Power and speed are the main highlights considered while comparing any design. Diminishing chip area is additionally truly impressive factor, designers need to recall when suggesting any novel design. 2x4 LP and LPI Decoders using 12T (Transistor) is used for conversion of binary inputs to associated output bits in a pattern. A novel design (CMOS logic and DVL logic) of 2x4 LP and LPI Decoders using 12T is proposed with area optimization, LP and high speed in this paper. Delay and power is evaluated between the novel design and CMOS logic. The novel design of 12T LP and LPI 2x4 Decoders is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 1.8V. The proposed method has been validated using Cadence 45 GPDK (Generic Product Design Key) Virtuoso Tool. [ABSTRACT FROM AUTHOR]

Optical power splitters (OPSs) are utilized extensively in integrated photonic circuits, drawing significant interest in research on power splitters with adjustable splitting ratios. This paper introduces a compact, low-loss 1 × 2 asymmetric multimode interferometric (MMI) optical power splitter on a silicon-on-insulator (SOI) platform. The device is simulated using the finite difference method (FDM) and eigenmode expansion solver (EME). It is possible to attain various output power splitting ratios by making the geometry of the MMI central section asymmetric relative to the propagation axis. Six distinct optical power splitters are designed with unconventional splitting ratios in this paper, which substantiates that the device can achieve any power splitter ratios (PSRs) in the range of 95:5 to 50:50. The dimensions of the multimode section were established at 2.9 × (9.5–10.9) μm. Simulation results show a range of unique advantages of the device, including a low extra loss of less than 0.4 dB, good fabrication tolerance, and power splitting ratio fluctuation below 3% across the 1500 nm to 1600 nm wavelength span. [ABSTRACT FROM AUTHOR]

This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the degradation of IC parameters. It describes the tests carried out on the reliability of controlled parameters of integrated circuit TPS54332, such as quiescent current, quiescent current in standby mode, resistance of the open key, and instability of the set output voltage in the whole range of input voltages and in the whole range of load currents. The calculated values of activation energies and acceleration coefficients for different test temperature regimes are given. As a result of the work done, sample rejection tests have been carried out on the TPS54332 IC under study. Experimental fail-safe tests were carried out, with subsequent analysis of the chip samples by the controlled parameter quiescent current. On the basis of the obtained experimental values, the values of activation energy and acceleration coefficient at different temperature regimes were calculated. The dependencies of activation energy and acceleration coefficient on temperature were plotted, which show that activation energy linearly increases with increasing temperature, while the acceleration coefficient, on the contrary, decreases. It was also found that the value of the calculated activation energy of the chip is 0.1 eV less than the standard value of the activation energy. [ABSTRACT FROM AUTHOR]

In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution. [ABSTRACT FROM AUTHOR]

Self-destructing chips have promising applications for securing data. This paper proposes a new concept of energetic diodes for the first time, which can be used for self-destructive chips. A simple two-step electrochemical deposition method is used to prepare ZnO/CuO/Al energetic diode, in which N-type ZnO and P-type CuO are constricted to a PN junction. This paper comprehensively discusses the material properties, morphology, semiconductor characteristics, and exploding performances of the energetic diode. Experimental results show that the energetic diode has typical rectification with a turn-on voltage of about 1.78 V and a reverse leakage current of about 3 x 10-4 A. When a constant voltage of 70 V loads to the energetic diode in the forward direction for about 0.14 s or 55 V loads in the reverse direction for about 0.17 s, the loaded power can excite the energetic diode exploding and the current rises to about 100 A. Due to the unique performance of the energetic diode, it has a double function of rectification and explosion. The energetic diode can be used as a logic element in the normal chip to complete the regular operation, and it can release energy to destroy the chip accurately. [ABSTRACT FROM AUTHOR]

With the continuous progress in integrated circuit technology, single-event effect (SEE) has become a key factor affecting the reliability of aerospace integrated circuits. Simulating fault injection using the computer simulation technique effectively reflects the SEE in aerospace integrated circuits. Due to various masking effects, only a small number of faults will result in errors; the traditional method of injecting one fault in one workload execution is inefficient. The method of injecting multiple faults in one workload execution will make it impossible to judge which fault results in errors because the propagation characteristic of SEE and faults may affect each other. This paper proposes an improved multi-point fault injection method to improve simulation efficiency and solve the problems of the general multi-point fault injection method. If one workload execution does not result in errors, multiple faults can be verified by one workload execution. If one workload execution results in errors, a specific grouping method can be used to determine which faults result in errors. The experimental results show that the proposed method achieves a good acceleration effect and significantly improves the simulation efficiency. [ABSTRACT FROM AUTHOR]

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion. [ABSTRACT FROM AUTHOR]

The article presents the information on authors involved in the journal.

Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date. [ABSTRACT FROM AUTHOR]

The dielectric loss of Cu with high thermal conductivity is large at high frequency, which cannot meet the performance requirements in high-integrated circuits. There is an urgent need for materials to reduce its dielectric loss. In this paper, the thermal conductivity and dielectric properties of the AlN coating-Cu substrate system were controlled by changing the N2 pressure. The results showed that the crystallinity of hcp-AlN in AlN coating increased significantly when the proportion of N2 pressure was increased. With the increase of the N2 pressure, the particle size on the surface and the roughness of the coating improved. The AlN coating prepared at high N2 pressure had high dielectric constant and low dielectric loss at high frequency compared to those of the coatings prepared at low N2 pressure. At the same time, the AlN coating prepared under high N2 pressure on the Cu substrate did not decrease the thermal conductivity of Cu substrate. The AlN-Cu system prepared in this paper had high thermal conductivity and good dielectric properties, providing theoretical guidance for integrated circuit packaging and capacitor applications. [ABSTRACT FROM AUTHOR]

The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations. [ABSTRACT FROM AUTHOR]

A physical unclonable function (PUF) is a technology designed to safeguard sensitive information and ensure data security. PUFs generate unique responses for each challenge by leveraging random deviations in the physical microstructures of integrated circuits (ICs), making it incredibly difficult to replicate them. However, traditional silicon PUFs are now susceptible to various attacks, such as modeling attacks using conventional machine learning techniques and reverse engineering strategies. As a result, PUFs based on new materials or methods are being developed to enhance their security. However, in the realm of survey papers, it has come to our attention that there is a notable scarcity of comprehensive summaries and introductions concerning these emerging PUFs. To fill this gap, this article surveys PUFs based on novel technologies in the literature. In particular, we first provide an insightful overview of four types of PUFs that are rooted in advanced technologies: bionic optical PUF, biological PUF, PUF based on printed electronics (PE), and PUF based on memristors. Based on the overview, we further discuss the evaluation results of their performance based on specific metrics and conduct a comparative analysis of their performance. Despite significant progress in areas such as limited entry and regional expertise, it is worth noting that these PUFs still have room for improvement. Therefore, we have identified their potential shortcomings and areas that require further development. Moreover, we outline various applications of PUFs and propose our own future prospects for this technology. To sum up, this article contributes to the understanding of PUFs based on novel technologies by providing an in-depth analysis of their characteristics, performance evaluation, and potential improvements. It also sheds light on the wide range of applications for PUFs and presents enticing prospects for future advancements in this field. [ABSTRACT FROM AUTHOR]

In this paper the design of power management integrated circuits for the energy harvesting of ultrasound waves in implanted biomedical devices is addressed. In particular, the paper focuses on the main building block of the power conversion stage which is represented by the AC/DC converter. After an in-depth analytical description of cross-coupled passive and active rectifiers, a detailed design procedure for the common-gate comparator is introduced. Then a comparison between the different discussed topologies is carried through simulation results using a 28-nm standard CMOS technology. The results provide useful design guidelines in choosing the best topology according to the design specifications. [ABSTRACT FROM AUTHOR]