Search

In this paper, the electrothermal coupling model of metal oxide resistive random access memory (RRAM) is analyzed by using a 2D axisymmetrical structure in COMSOL Multiphysics simulation software. The RRAM structure is a Ti/HfO2/ZrO2/Pt bilayer structure, and the SET and RESET processes of Ti/HfO2/ZrO2/Pt are verified and analyzed. It is found that the width and thickness of CF1 (the conductive filament of the HfO2 layer), CF2 (the conductive filament of the ZrO2 layer), and resistive dielectric layers affect the electrical performance of the device. Under the condition of the width ratio of conductive filament to transition layer (6:14) and the thickness ratio of HfO2 to ZrO2 (7.5:7.5), Ti/HfO2/ZrO2/Pt has stable high and low resistance states. On this basis, the comparison of three commonly used RRAM metal top electrode materials (Ti, Pt, and Al) shows that the resistance switching ratio of the Ti electrode is the highest at about 11.67. Finally, combining the optimal conductive filament size and the optimal top electrode material, the I-V hysteresis loop was obtained, and the switching ratio Roff/Ron = 10.46 was calculated. Therefore, in this paper, a perfect RRAM model is established, the resistance mechanism is explained and analyzed, and the optimal geometrical size and electrode material for the hysteresis characteristics of the Ti/HfO2/ZrO2/Pt structure are found. [ABSTRACT FROM AUTHOR]

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A "sandwich" capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays' benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). [ABSTRACT FROM AUTHOR]

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint. [ABSTRACT FROM AUTHOR]

In this paper, the designs of ternary digital circuits are discussed. The ternary logic is a better choice over conventional logics due its extraordinary offers such as high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented in this paper to design the ternary circuits using graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The dimer line of graphene nanoribbon (GNR) is used to control the threshold voltage of GNRFETs. The RRAM is used because it has multilevel cell capacity that enables the multiple resistance state storage in a single cell. The ternary logic basic circuits such as standard ternary inverter (STI), NAND and NOR circuits are proposed. In addition, ternary half adder circuit is designed that helps to develop the complex circuits. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). Furthermore, the obtained circuit performances are compared with carbon nanotube FETs (CNTFETs)-based and RRAM-based circuits. The comparison results show that the proposed GNRFET and RRAM circuits achieved 46.11% of overall performance improvement over the CNTFET and RRAM circuits. Furthermore, line edge roughness (Pr) effect on the proposed STI and half adder circuit performance is investigated. The delay values are increased, and the power and PDP values are decreased for the higher Pr values. The effect of process, voltage and temperature (PVT) variations on proposed STI and half adder circuits is also performed to analyze the performance. It noticed that the proposed STI and half adder circuits show minimum variation on performance for the PVT variations. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM) is often considered as a strong candidate for storing the weights in non-von Neumann neuromorphic computing systems. This paper studies how nonideal memory characteristics, which include programing error, read fluctuation, and retention, affect the inference accuracy of the analog ReRAM neural networks by incorporating memory characteristics extracted from 1-Mb ReRAM into a simulated inference-only neural network. This paper also shows that the different layer in the network can tolerate different amount of such imperfects. We learned four key points: 1) the conductance range of memory with less relative fluctuation is preferred for designing the weight-conductance mapping; 2) the control of programing error is essential for high inference accuracy; 3) retention-induced conductance drift can be fatal to the neuromorphic system. A compensation scheme is proposed in this paper which can effectively recover the inference accuracy; and 4) for multilayer networks, avoiding weight errors in the front layers can help to maintain the inference accuracy by reducing calculation error which may otherwise accumulate and pass down the networks. The concepts and approaches of this paper can also be applied to evaluate other types of nonvolatile memories for artificial neural networks. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

In this paper, the read margin (RM) and write power (WP) of 3-D vertical resistive random access memory (VRRAM) are analyzed by considering the variation in RRAM cell (self-rectifying cell) characteristics. To demonstrate the cell variation effect on a large 3-D VRRAM array, we develop a modified lumping method in HSPICE simulator and show that this method substantially reduces the computation time while maintaining high accuracy. Read and write performances including cell variation are investigated according to various array sizes and RRAM characteristics. A large distribution of cell current reduces the RM but hardly affects the WP. Moreover, in 3-D VRRAM with a small number of wordline (WL) layers, a large on/off ratio (RHRS/RLRS) is advantageous for improving the RM and reducing the variation effect. In contrast, a large on/off ratio has little effect on the RM in 3-D VRRAM with many WL layers. This difference occurs because the increased leakage induced in the half-selected cells mainly affects the RM, and the half-selected cells are located in the selected vertical pillar in 3-D VRRAM. [ABSTRACT FROM AUTHOR]

Metal-organic frameworks (MOFs) have attracted considerable interests for sensing, electrochemical, and catalytic applications. Most significantly, MOFs with highly accessible sites on their surface have promising potential for applications in high-performance computing architecture. In this paper, Mg-MOF-74 (a MOF built of Mg(II) ions linked by 2,5-dioxido-1,4-benzenedicarboxylate (DOBDC) ligands) and graphene oxide composites (Mg-MOF-74@GO) were first used as an active layer to fabricate ternary memory devices. A comprehensive investigation of the multi-bit data storage performance for Mg-MOF-74@GO composites was discussed and summarized. Moreover, the structure change of Mg-MOF-74@GO after introducing GO was thoroughly studied. The as-fabricated resistive random access memory (RRAM) devices exhibit a ternary memristic behavior with low SET voltage, an RHRS/RIRS/RLRS ratio of 103:102:1, superior retention (>104 s), and reliability performance (>102 cycles). Herein, Mg-MOF-74@GO composite films in constructing memory devices were presented with GO-mediated ternary memristic properties, where the distinct resistance states were controlled to achieve multi-bit data storage. The hydrogen bonding system and defects of GO adsorbed in Mg-MOF-74 are the reason for the ternary memristic behavior. The charge trapping assisted hopping is proposed as the operation mechanism, which is further confirmed by XRD and Raman spectra. The GO-mediated Mg-MOF-74 memory device exhibits potential applications in ultrahigh-density information storage systems and in-memory computing paradigms. [ABSTRACT FROM AUTHOR]

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS 2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

The switching properties of Te and TeTiW top electrodes (TEs) on TiW/SiN/TiN resistive switching memory devices are explored in this paper. The TeTiW TE device exhibits more favorable bipolar resistive switching behavior because of the decrease in binding energy after its use. This finding is confirmed through X-ray photoelectron spectroscopy analyses. The filament of the TeTiW TE device is metal like after forming, and the reset process corresponds with the thermal-dissolution mechanism. A physical model based on a Te filament is constructed to explain such phenomena. The TeTiW TE device provides the excellent endurance of more than 104 cycles, with an ON/OFF ratio of 500. The improvement can be attributed to the filament’s robustness during the forming and set processes, which prevent its diffusion even at high temperature. The device also features long retention for up to 104 s at 225 °C without stress, and 104 s at 85 °C with stress of −0.3 V. Therefore, it has high potential for high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45 nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods. [ABSTRACT FROM AUTHOR]

Despite the great promises that the resistive random access memory (ReRAM) has shown as the next generation of non-volatile memory technology, its crossbar array structure leads to a severe sneak path interference to the signal read back from the memory cell. In this paper, we first propose a novel belief propagation (BP) based detector for the sneak path interference in ReRAM. Based on the conditions for a sneak path to occur and the dependence of the states of the memory cells that are involved in the sneak path, a Tanner graph for the ReRAM channel is constructed, inside which specific messages are updated iteratively to get a better estimation of the sneak path affected cells. We further combine the graph of the designed BP detector with that of the BP decoder of the polar codes to form a joint detector and decoder. Tailored for the joint detector and decoder over the ReRAM channel, effective polar codes are constructed using the genetic algorithm. Simulation results show that the BP detector can effectively detect the cells affected by the sneak path, and the proposed polar codes and the joint detector and decoder can significantly improve the error rate performance of ReRAM. [ABSTRACT FROM AUTHOR]

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM. [ABSTRACT FROM AUTHOR]

Artificial neural network‐based computing is anticipated to surpass the von Neumann bottleneck of traditional computers, thus dramatically boosting computational efficiency and showing a wide range of promising applications. In this paper, sol−gel deposition was used to prepare thin films of samarium‐doped hafnium dioxide (Sm:HfO2). When Sm is doped at a concentration of 4%, it mimics biological synapses; meantime, by voltage scanning, an obvious mimicry of resistive switching can be detected, demonstrating that the technology may be applied to simulate biological synapse characteristics, including long‐term potentiation (depression), short‐term potentiation (depression), paired‐pulse facilitation, and learning rules of spike‐time‐dependent plasticity. Additionally, a pulsed neural network is built on the MNIST dataset to test the memristor's capacity to handle visual input. The findings show the possibility of synthetic synapses in artificial intelligence systems that integrate neuromorphic computing with synaptic brain activity. [ABSTRACT FROM AUTHOR]

This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented. [ABSTRACT FROM AUTHOR]

Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics. [ABSTRACT FROM AUTHOR]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Additionally, no additional memory usage is required to avoid the need for a large amount of data transportation in convolution computation. Partial quantization is introduced to reduce the accuracy loss. The proposed architecture can substantially reduce the overall power consumption and accelerate computation. The simulation results show that the image recognition rate for the Convolutional Neural Network (CNN) algorithm can reach 284 frames per second at 50 MHz using this architecture. The accuracy of the partial quantization remains almost unchanged compared to the algorithm without quantization. [ABSTRACT FROM AUTHOR]

In this paper, we present the results of our systematic investigations of the resistive switching characteristics of HfO2-based metal–insulator–metal structures using four different metal bottom electrode (BE) materials, namely Au, Al, Pt and Cu. Ag is used as the top electrode for all these resistive random access memory devices. On one hand, Au and Pt show lower set and reset voltages, whereas the Pt electrode has a higher resistance ratio (Roff/Ron) ~ 105). On the other hand, Al and Cu exhibit multilevel switching during the reset process. Thus, the oxygen affinity of the BE is expected to result in the formation of an interfacial layer with the active (HfO2) layer. Furthermore, conduction mechanisms have been studied for the various regions in the high resistance state (HRS) curves of all these devices. It is found that the Poole–Frenkel effect is more dominant at higher voltages (> 1 V) in the HRS curve. Therefore, it is essential to elucidate the appropriate BE material and optimum active switching layer to understand the conduction mechanisms for the resistive switching phenomenon. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. [ABSTRACT FROM AUTHOR]

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented. [ABSTRACT FROM AUTHOR]

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry's introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) is a promising architecture to design various types of neural network accelerators as it ensures the efficiency of computation together with Resistive Random Access Memory (ReRAM). ReRAM has now become a promising solution to enhance computing efficiency due to its crossbar structure. In this paper, a ReRAM-based PIM neural network accelerator is addressed, and different kinds of methods and designs of various schemes are discussed. Various models and architectures implemented for a neural network accelerator are determined for research trends. Further, the limitations or challenges of ReRAM in a neural network are also addressed in this review. [ABSTRACT FROM AUTHOR]

Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 \mu \textA to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively. [ABSTRACT FROM PUBLISHER]

We study in detail the impact of alloying HfO2 with Al (Hf1–xAl2xO2+x) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed comprehensive diffusion barrier calculations in HfO2, Hf1–xAl2xO2+x, and Hf1–xTixO2 relative to the oxygen vacancy ( Vo ) movement involved in low-resistance state ( R\mathrm{\scriptscriptstyle ON} ) thermal stability. Calculations are performed at the best level using ab initio techniques. This paper provides an insight on the improved R\mathrm{\scriptscriptstyle ON} stability of our Hf1–xAl2xO2+x-based RRAM devices and predicts the degraded retention of Hf1–xTixO2-based RRAM measured in the literature. Our theoretical calculations link the origin of R\mathrm{\scriptscriptstyle ON} retention failure to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in HfO2-based RRAM. [ABSTRACT FROM PUBLISHER]

Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

Electrochemical-metallization-type resistive random access memories (ReRAMs) show promising performance as next-generation nonvolatile memory. In this paper, the Cu chemical displacement technique (CDT) is used to form the bottom electrode of ReRAM devices. Compared with conventional deposition methods, the Cu-CDT method has numerous advantages for ReRAM fabrication, including low cost, low temperature fabrication, and the provision of unconsolidated Cu film and large surface roughness. Moreover, the Cu-CDT method is a favorable candidate for overcoming the Cu etching problem and is thus suitable for fabricating ReRAM devices. Using this technique, the surface morphology of a thin Cu film can be easily controlled. The obtained results show that the electric fields during the Forming and SET operations decreased, and the on-state current increased in the RESET operation, as the Cu-CDT displacement time was increased. The Cu-CDT samples exhibited a low operation field, large memory window (>106), and excellent endurance switching cycle characteristics. Moreover, this paper proposes a model to explain the electrical characteristics of ReRAM, which are dependent on the surface morphology. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the link between various resistive memory (RRAM) electrical characteristics: endurance, window margin (WM), and retention. For this purpose, several RRAMs are characterized using various resistive layers and bottom electrodes. By focusing on one technology and optimizing programming conditions (current, voltage, and time), we establish a tradeoff between endurance and WM. Then, by changing memory stack, we demonstrate the correlation between endurance plus window marging improvement and retention degradation. Studying this last feature from a material point of view, we analyze different oxides by density functional theory. We realize a systematic review for possible exchanges of species between resistive layer and Cu-based top electrode and study their diffusion. This provides insights on conductive filament composition in different stacks. Combining previous experiments and simulations, we propose a link between memory characteristics and material microscopic parameters, through the ion energy migration barrier. Finally, we extract how endurance, WM, and retention are correlated to material properties and electrical parameters in order to choose the suitable material for a defined application using the RRAM technology. [ABSTRACT FROM AUTHOR]

Bismuth-layered oxides are a very important class of ferroelectric materials. Due to their special structure, they have outstanding features in many aspects, such as high Curie temperature, large spontaneous polarization, polarization stability to temperature, high voltage resistance, low dielectric loss, and excellence. Due to its antifatigue properties, the system is very suitable for applications in nonvolatile random access memory and high-temperature sensors. The purpose of this paper is to study the application of the performance and modification of bismuth-layered ferroelectric materials in sports scientific research. Proposed the combination of new materials and sports scientific research projects. This article uses sample analysis and (the comparative experiment method is a method to compare the experimental group and the control group to illustrate the superiority of the experiment) comparative experiment methods, sets up an experimental group and a control group, summarizes the algorithm rules through the study of the microscopic properties of nanomaterials, and designs a numerical simulation program. The experimental results in this article show that after receiving hyperbaric oxygen recovery in the first week, the heart rate of the experimental group subjects has a significant change, which is significantly lower than the initial value (p < 0.05), from 58.0 to 53.0, The higher pressure oxygen had a very significant drop before recovery, from 62.9 to 53.0. In the second week and the third week, the heart rate index decreased significantly after 1 hour of hyperbaric oxygen recovery (p < 0.01), from 54.3 to 49.3 and 56.1 to 52.4, respectively. After the fourth week of intensity training, the heart rate increased significantly from the initial value (p < 0.05), from 49.6 to 55.2. After 1 hour of hyperbaric oxygen recovery, there was a significant decrease compared with before the hyperbaric oxygen recovery (p < 0.05), dropped from 55.2 to 53.1. Illustrate the success of the experimental results. It also completed the subject of interaction and combination of the performance and modification of bismuth-layered ferroelectric materials in sports scientific research. [ABSTRACT FROM AUTHOR]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1]. An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS. [ABSTRACT FROM AUTHOR]

Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable nonvolatile memory technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<±1 V) at fast time-scales (≍10–100 ns) that make them an attractive option for not only off-chip data storage but also for on-chip embedded memory applications. ReRAM devices have also been explored for applications as reconfigurable switches in field programmable gate arrays (FPGAs). The random variabilities in the switching performance of ReRAM has been exploited to design Physically Unclonable Function (PUF) for hardware authentication, trust, and security. However, intrinsic vulnerabilities in ReRAM devices and its implications are not well-understood. Therefore, there is an urgent need to understand these so that the ReRAM-based circuits can be made robust against such attacks. This paper discusses our research on understanding the vulnerabilities in ReRAM through experimental studies and its implications on ReRAM based PUF operations. The Process, Voltage, Temperature (PVT) variabilities in ReRAM is experimentally studied and modeled. Some other ReRAM specific vulnerabilities, such as insertion of parasitic capacitances and Trojans by adversaries and its impact on ReRAM switching behavior is discussed. Based on experimental studies, models are created to capture these behaviors in ReRAM. Using these models, a 1 KB array of ReRAM devices in a crossbar architecture and its behavior is simulated. The challenge–response pairs of these ReRAM-based arrays were studied under ideal Trojan free conditions as well as with vulnerabilities models of ReRAM. Potential solutions are then proposed to make the PUF architecture and ReRAM devices more resistant to these vulnerabilities. [ABSTRACT FROM AUTHOR]

Recent studies of resistive switching devices with hexagonal boron nitride (h-BN) as the switching layer have shown the potential of two-dimensional (2D) materials for memory and neuromorphic computing applications. The use of 2D materials allows scaling the resistive switching layer thickness to sub-nanometer dimensions enabling devices to operate with low switching voltages and high programming speeds, offering large improvements in efficiency and performance as well as ultra-dense integration. These characteristics are of interest for the implementation of neuromorphic computing and machine learning hardware based on memristor crossbars. However, existing demonstrations of h-BN memristors focus on single isolated device switching properties and lack attention to fundamental machine learning functions. This paper demonstrates the hardware implementation of dot product operations, a basic analog function ubiquitous in machine learning, using h-BN memristor arrays. Moreover, we demonstrate the hardware implementation of a linear regression algorithm on h-BN memristor arrays. [ABSTRACT FROM AUTHOR]

Neural networks have been widely deployed in sensor networks and IoT systems due to the advance in lightweight design and edge computing as well as emerging energyefficient neuromorphic accelerators. However, adversary attack has raised a major threat against neural networks, which can be further enhanced by leveraging the natural hard faults in the neuromorphic accelerator that is based on resistive random access memory (RRAM). In this paper, we perform a comprehensive fault-aware attack analysis method for RRAM-based accelerators by considering five attack models based on a wide range of device- and circuit-level nonideal properties. The research on nonideal properties takes into account detailed hardware situations and provides a more accurate perspective on security. Compared to the existing adversary attack strategy that only leverages the natural fault, we propose an initiative attack based on two soft fault injection methods, which do not require a high-precision laboratory environment. In addition, an optimized fault-aware adversary algorithm is also proposed to enhance the attack effectiveness. The simulation results of an MNIST dataset on a classic convolutional neural network have shown that the proposed faultaware adversary attack models and algorithms achieve a significant improvement in the attacking image classification. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

This paper investigated the performance of flexible resistive random access memory devices based on simple spin-coated sol–gel-derived strontium titanate nickelate (STN) thin films on polyethylene terephthalate substrate. A high on/off ratio of 10^5 and a uniform current distribution were demonstrated. The strong bonding between bidentate ligands of nickel (II) acetylacetone and titanium metal ion enabled the chelation effect, which contributed to the stability of the STN thin film, especially for moisture resistivity. Fourier transform infrared spectroscopy analysis was utilized to examine the effects on the resistive switching behaviors after 90 days under an atmospheric environment according to the chelation effect of the STN thin films. The devices were fabricated on a flexible plastic substrate, and they exhibited excellent durability upon repeated bending tests. They demonstrated good potential application for flexible and low-cost memory devices. [ABSTRACT FROM PUBLISHER]

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size. [ABSTRACT FROM AUTHOR]

Resistive random access memory (RRAM) is a promising candidate for next generation nonvolatile memory technology. In this paper, electrothermal simulation in 3-D RRAM arrays is performed by using our in-house developed finite difference algorithm, which is validated by comparing the simulated temperature distribution with its counterpart obtained by commercial software. Both crossbar RRAM array and vertical RRAM array are studied comprehensively with careful consideration of the temperature-dependent constitute parameters. Simulations show that the temperature and thermal crosstalk are sensitive to the size and shape of conductive filament, which can further limit the scaling potential of RRAM array through affecting its reliability, such as retention time, current leakage, and so on. Scaling behavior of 3-D RRAM array is studied, and optimization guidance for reducing thermal crosstalk is proposed. The fabrication inaccuracy resulted cell offset has also been examined for investigation of thermal crosstalk. [ABSTRACT FROM PUBLISHER]