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The article presents a series of abstracts of articles on computer programs for use in marketing research, including "COFIS: An IBM 360/65 FORTRAN IV Program for Configural Scoring," by Frank J. Carmone, Paul E. Green and Patrick J. Robinson, "TOSCA-9: An IBM 360/75 FORTRAN IV Program for Nonmetric Multidimensional Scaling," by Forrest Young and "EMD: A FORTRAN IV Program for Nonmetric (Elastic) Multidimensional Data Reduction," by Victor E. McGee.

Copyright of International Journal of Medicine & Science of Physical Activity & Sport / Revista Internacional de Medicina y Ciencias de la Actividad Física y del Deporte is the property of Revista Internacional de Medicina y Ciencias de la Actividad Fisica y del Deporte and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The Cell Broadband Engine® (Cell/B.E.) processor is a hybrid IBM PowerPC® processor. In blade servers and PCI Express® card systems, it has been used primarily in a server context, with Linux® as the operating system. Because neither Linux as an operating system nor a PowerPC processor-based architecture is the preferred choice for all applications, some installations use the Cell/B.E. processor in a coupled hybrid environment, which has implications for the complexity of systems management, the programming model, and performance. In the directCell approach, we use the Cell/B.E. processor as a processing device connected to a host via a PCI Express link using direct memory access and memory-mapped I/O (input/output). The Cell/B.E. processor functions as a processor and is perceived by the host like a device while maintaining the native Cell/B.E. processor programming approach. We describe the problems with the current practice that led us to the directCell approach. We explain the challenge in programming, execution control, and operation on the accelerators that were faced during the design and implementation of a prototype and present solutions to overcome them. We also provide an outlook on where the directCell approach promises to better solve customer problems. [ABSTRACT FROM AUTHOR]

Object-based storage is the natural evolution of the block storage interface, aimed at efficiently and effectively meeting the performance, reliability, security, and service requirements demanded by current and future applications. The object-based storage interface provides an organizational container, called an object, into which higher-level software (e.g., file systems, databases, and user applications) can store both data and related attributes. In 2004, the ANSI (American National Standards Institute) T10 Standards body ratified an Object-based Storage Device (OSD) command set for SCSI (Small Computer System Interface) storage devices that implements the OSD interface. This paper describes the rationale for OSDs, highlights the ANSI T10 OSD V1.0 interface, and presents three OSD implementations: an OSD from Seagate, an IBM object-based storage prototype (ObjectStone), and the Panasas object-based distributed storage system. [ABSTRACT FROM AUTHOR]

The very rapid growth of data-intensive computing makes it attractive to perform computations locally, where data is stored. Large storage systems based on standard system technologies with server virtualization capabilities make it feasible to deploy application-specific processing onto the storage system, without jeopardizing the availability of the core storage service or degrading performance. Moreover, price and capacity differences between mainframes and these storage systems make this deployment attractive. We describe the design of a prototype system by which the IBM DS8000 storage system can host application extensions, called adjuncts, that improve the operation of IBM z/OS (mainframe) applications. These extensions process large amounts of data in operations such as searching, sorting, and indexing so that the host application need not even access most of the data. The benefits of application extensions result from applying system resources more efficiently. Application processing at the storage system magnifies the total throughput that can be achieved by the host application. Furthermore, by avoiding the transmission of large volumes of data through multiple hardware and software layers, processing often takes a shorter time at a lower cost. [ABSTRACT FROM AUTHOR]

Although decimal arithmetic is widely used in commercial and financial applications, the related computations are handled in software. As a result, applications that use decimal data may experience performance degradations. Use of the newly defined decimal floating-point (DFP) format instead of binary floating-point is expected to significantly improve the performance of such applications. System z9™ is the first IBM machine to support the DFP instructions. We present an overview of this implementation and provide some measurement of the performance gained using hardware assists. Various tools and techniques employed for the DFP verification on unit, element, and system levels are presented in detail. Several groups within IBM collaborated on the verification of the new DFP facility, using a common reference model to predict DFP results. [ABSTRACT FROM AUTHOR]

The design and implementation of the z/VM® SCSI (Small Computer System Interface) I/O subsystem is described, z/VM is an operating system that provides multiple virtual IBM System z™ machines on a single IBM System z computer. The approach adopted herein allows the reuse of entire device drivers from AIX 5L™, a completely different operating system, essentially unchanged. AIX 5L is the IBM UNIX® operating system for the IBM System p™ platform. The design, and much of the implemented code that allows the incorporation of such "foreign" device drivers, is independent of both z/VM and AIX 5L and could potentially be used in other operating system environments. [ABSTRACT FROM AUTHOR]

Our methods for simulating host firmware of the IBM System z9™ facilitated rapid development from first power-on of the system to achieving a platform with a functional operating system. Hundreds of code bugs were eliminated before the code was run on System z9 hardware for the first time. This paper describes the methods used in host firmware simulation for early and efficient firmware tests. The central clement for firmware simulation is the Central Electronic Complex Simulator (CECSIM), which offers new facilities to manage the hardware of the simulated system. This management includes concurrent configuration changes of processors, memory, and I/O along with the ability to automatically test complex system functions. To verify correct implementation of the z/Architecture™, we introduced a new test-case framework called the Verification Interface for System Architecture, or VISA, which is used in simulations as well as on the actual system. All of these features are used separately and in combination. A comprehensive and flexible regression environment ensures periodic execution of the test scenarios, and code path coverage measurements show the degree to which the code was actually verified. [ABSTRACT FROM AUTHOR]

When the PL8 64-bit GNU compiler collection front end was introduced with the IBM z990 system, it laid the foundation to move toward an open-standard development environment for the i390 layer of IBM System z™ host firmware. However, when the z990 system was developed, the proprietary project development library system and the table of contents object file format for i390 code were still being used. With the IBM System z9™, we have moved to a fully open-standard development environment. This paper describes the steps we took to get there, to improve code performance, development efficiency, and regression testing, and to develop base functionality for important System z9 features such as enhanced driver maintenance. We also discuss plans to further enhance the development environment for future systems. [ABSTRACT FROM AUTHOR]

The reliability, availability, and serviceability goal for an IBM zSeries® system is to provide 24-hour-per-day, 365-day-per-year service with reduced system downtime. The continuous reliable operation rate has been improved with every new zSeries release by using error prevention, error detection, error recovery, and other methods that contribute to avoiding unplanned interruptions. Until now, planned downtime--for example, the time needed to upgrade a zSeries to the next firmware driver--had not yet been addressed. We developed the concurrent driver upgrade (CDU) feature so that customers could acid new functions without downtime. It is now possible to upgrade the zSeries firmware engineering change (EC) driver to the next EC level without any performance impact during the upgrade. This paper describes the motivation and strategy of the CD U and describes its use. [ABSTRACT FROM AUTHOR]

This paper describes a fully redundant clock generation and distribution approach with a fully dynamic switchover capability and concurrent repair. It highlights the challenges as the design evolved from a single source, to a "cold" standby backup, and finally to a fully redundant transparent switchover with no interruption of the workloads running on an IBM System z9™. The function split between hardware and the various levels of firmware is described, including the methods to determine the defect component in the clock distribution paths. Finally, we describe the joint effort with a major chip technology vendor to design and develop the necessary circuitry, according to the z9™ requirements, for clock synchronization and switching. [ABSTRACT FROM AUTHOR]

Although part of the IBM System z™ strategy is to improve design and development processes to prevent errors from escaping to the field, improving recovery is another element in the strategy to keep a machine up and running should an error occur. The z9™ continues on an evolutionary path of enhancing I/O subsystem (IOSS) recovery to further advance the reliability, availability, and serviceability (RAS) of System z platforms. This paper presents an overview of recovery and how it interacts with other RAS functions--such as error-detection mechanisms in hardware, including automatic identification and recovery of failing elements--up to the point in time prior to the advent of the z9. It then presents the innovations to IOSS recovery and error detection in the z9 that further improve machine availability. The recovery infrastructure, which significantly reduces recovery time and makes recovery much less dependent on machine scaling for this and future generations of System z servers, is described. Also described are such innovative uses of this new infrastructure as improvements in error detection related to elusive firmware problems seen in prior machines, the ability to detect and recover from firmware hangs or lockups related to inadvertently leaving control blocks locked, and the capability to perform recovery in parallel by multiple system-assist processors. [ABSTRACT FROM AUTHOR]

The IBM System z9™ introduces the enhanced book availability (EBA) feature to reduce the number of planned system outages. Included as part of the EBA feature is the concurrent book replacement (CBR) function, which allows a single book in a multi-book server to be concurrently removed from the system in order for service personnel to perform a repair or to physically upgrade the hardware on the book. This repaired or upgraded book is then concurrently replaced and reintegrated into the server configuration. In this paper, we describe the benefits that the concurrent book replacement function offers a customer during a planned repair or upgrade of the System z9. We also describe a tool, developed to analyze the server in order to determine whether the server is "prepared" for the concurrent book replacement operation, and we provide an overview of the actions performed by this tool. The paper also contains a description of the concurrent book replacement operation, with an emphasis on the unique functions developed as part of this design. [ABSTRACT FROM AUTHOR]

The IBM 374x Communication Controllers, and the NCP (network control program) software that runs on them, have been at the center of the IBM SNA (Systems Network Architecture) for many years. However, the 374x hardware is no longer being produced. In order to continue to offer IBM customers various functions provided by the NCP product, IBM has developed a Communication Controller for Linux® (CCL) for the IBM System z™. CCL is a software program that emulates the 374x hardware, enabling the NCP to function in Linux. IBM customers now have the ability to migrate their NCP product to a Linux partition on System z. The current NCP product, running on an IBM 374x Communication Controller, supports both host channel and network attachment. The channel protocol used for the host-channel support is referred to as channel data link control (CDLC). In order to provide the System z9™ host operating systems with the ability to attach to the new CCL NCP over a channel interface, a new channel adapter is required. The new innovative Open Systems Adapter for NCP (OSN) channel support provided by the OSA-Express2 allows various operating systems on the same System z9 to attach "internally" to the CCL without using any external network or channel fabric. [ABSTRACT FROM AUTHOR]

IBM has offered hardware-based cryptographic processors for its mainframe computers for nearly thirty years. Over that period, IBM has continued to update both the hardware and software, providing added features, higher performance, greater physical security, and improved management features. This commitment continues with the System z9™, as demonstrated by the two improvements described in this paper. The first part of the paper describes enhancements to the System z9 to configure and control cryptographic features. The second part describes a new method for the cryptographic coprocessors to securely manage keys which are distributed to remote devices that are not necessarily in secure or well-controlled environments. [ABSTRACT FROM AUTHOR]

With the addition of IBM System z™ application assist processors (zAAPs) and integrated information processors (zIIPs) to the portfolio of special-purpose IBM System z processors, the reinvention of the IBM mainframe continues. Jointly, zAAPs and zIIPs provide significant IBM System z9™ integrated and cost-effective processing cycles for today's strategic Java™ and DB2® for z/OS® programming platforms which are increasingly fundamental to enterprise-class business environments. Overviews of zAAPs and zIIPs are presented that describe their functionality, design, and use by the z/OS operating system to achieve the execution of both Java and z/OS DB2 programming functions. [ABSTRACT FROM AUTHOR]

Cycle-time targets were set for the IBM System z9™ processor subsystem prior to building the system, and achieving these targets was one of the biggest challenges we faced during hardware development. In particular, although the processor-subsystem cycle-time improvement was driven primarily by the technology migration from CMOS 9S (130-nm lithography) for the prior IBM System z990 to CMOS 10SO (90-nm lithography)for the new system, the cooling capability for the System z9 resulted from a direct migration of the System z990 implementation with very limited improvements. The higher device current leakage and power associated with the technology migration, combined with the fixed cooling capability, created a technology challenge in which the subsystem cycle time and performance were potentially limited by cooling capability. Our solution emphasized silicon technology development, chip design, and hardware characterization and tuning. Ultimately, the System z9 processor subsystem achieved operation at 1.7 GHz, which exceeded the original target. [ABSTRACT FROM AUTHOR]

In this paper, the authors introduce the concept of zero-change netlist transformations (ZCNTs) to: 1) quantify the suboptimality of existing placers on artificially constructed instances and 2) ‘partially’ quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds to the suboptimality gap. Given a netlist and its placement from a placer, a class of netlist transformations that synthesizes a different netlist from the given netlist is formally defined, but yet the new netlist has the same half-perimeter wire length (HPWL) on the given placement. Furthermore, and more importantly, the optimal HPWL value of the new netlist is no less than that of the original netlist. By applying the transformations and reexecuting the placer, any deviation in HPWL as a lower bound to the gap from the optimal HPWL value of the new synthesized netlist can be interpreted. The transformations allow us to: 1) increase the cardinality of hyperedges; 2) reduce the number of hyperedges; and 3) increase the number of two-pin edges, while maintaining the placement HPWL constant. It is developed here methods that apply ZCNTs to synthesize netlists having typical netlist statistics. Furthermore, an approach to estimate the suboptimality of other metrics, such as rectilinear minimum-spanning tree (RMST) and minimum-Steiner tree, is extended. Using these transformations, the suboptimality of some of the existing academic placers (FengShui, Capo, mPL, Dragon) is studied on synthesized netlists from the IBM benchmarks with instances ranging from 10k to 210k placeable instances. The results show that current placers exhibit suboptimal behavior to ZCNTs with varying degree according to the placer. Systematic suboptimality deviations in HPWL and RMST are displayed on the synthesized netlists from IBM (version 1) benchmarks. The specific nature of the transformations points out troublesome netlist structures and possible directions for improvement in the existing placers. [ABSTRACT FROM AUTHOR]

Focuses on asynchronous transfer mode (ATM) technology. Description of ATM; Networking requirements; ATM standards; Tutorial on ATM technology; Overview of the International Business Machines (IBM) Corp.'s ATM product family; Description of the IBM 8260 Intelligent Switching Hub.

This article discusses the applications of International Business Machines (IBM) to educational research. The IBM machines include a large variety of punches, sorters, accounting machines, auxiliary machines and special devices. The less well-known machines are the alphabetical interpreter, which prints punched information across a card. In addition, the IBM machines include the test scoring machine with its graphic item counter and the aggregate weighting device. The machines, in general, make for greater speed in recording, classifying and tabulating data and in computing statistics.

The article discusses the development of central processing units (CPUs) which incorporate embedded graphics circuitry. The expectation that CPUs with integrated graphics processing capability will supplant motherboard-based integrated graphics processor (IGP) chipsets and largely eradicate IGPs' share of the computer-graphics market by the year 2013 is noted. A history of graphics hardware for personal computers is also presented, mentioning that the first dedicated graphics processing unit (GPU) was found on the IBM Monochrome Display Adapter (MDA) in 1981.

The article discusses the development of a computer program known as the dynamic multipliers (DYMULT). The DYMULT is a computer program utilizing a computer algorithm configured to measure the impact, interim and total multipliers of a simple linear simultaneous model with lags and checks the stability condition of the system of equations in econometrics. The functional equation of a simple lag linear equations model is presented comprising the column vector of the endogenous over a period of time. The algorithm used in the program utilized routines from the International Business Machines Corp.'s scientific subroutine package.