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The development of thin film transistor (TFTs) based integrated circuits on flexible substrates promise interesting approaches to human interface systems. Recently TFTs have been fabricated on textured surfaces such as textiles, paper, artificially corrugated or dimpled substrates, threads and fibers. This can result in the TFTs metal-insulator-semiconductor (MIS) stack being significantly distorted from a planar zero-curvature geometry to having non zero and potentially high curvature. Although the direct deposition on textured surfaces do not result in mechanical stress (as for example in bending, buckling or wrinkling), the geometry of high curvature can significantly influence the current voltage characteristics of the TFT. Here we present a closed form analytical model describing the geometrical impact of high curvature on the electrical performance of the TFT. Models are obtained from the solution to the Poisson-Boltzmann equation in polar co-ordinates and are verified using TCAD simulations. The techniques to generalize the results to adapt to any texture and semiconducting material are also discussed with experimental verification. This work forms an analytical basis to understand the impact of curvature on the electrostatics of the MIS stack and the current voltage characteristics of the TFT.