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A high-performance Deep Neural Network (DNN) model is a valuable intellectual property (IP) since designing and training such a model from scratch is very costly. Model transfer learning, compression and retraining are commonly used by pirates to evade detection or even redeploy the pirated models for new applications without compromising performance. This paper presents a novel non-intrusive DNN IP fingerprinting method that can detect pirated models and provide a nonrepudiable and irrevocable ownership proof simultaneously. The fingerprint is derived from projecting a subset of front-layer weights onto a model owner identity defined random space to enable a distinguisher to differentiate pirated models that are used in the same application or retrained for a different task from originally designed DNN models. The proposed method generates compact and irrevocable fingerprints against model IP misappropriation and ownership fraud. It requires no retraining and makes no modification to the original model. The proposed fingerprinting method is evaluated on nine original DNN models trained on CIFAR-10, CIFAR-100, and ImageNet-10. It is demonstrated to have the highest discriminative power among existing fingerprinting methods in detecting pirated models deployed for the same and different applications, and fraudulent model IP ownership claims. National Research Foundation (NRF) Submitted/Accepted version This research is supported by the National Research Foundation, Singapore, under its National Cybersecurity R&D Programme/Cyber- Hardware Forensic & Assurance Evaluation R&D Programme (Award: CHFA-GC1-AW01).

Peer to Peer (P2P) or direct connection IoT has become increasingly popular owing to its lower latency and higher privacy compared to database-driven or server-based IoT. However, wireless vulnerabilities raise severe concerns on IoT device-to-device communication. This is further aggravated by the challenge to achieve lightweight direct mutual authentication and secure key exchange between IoT peer nodes in P2P IoT applications. Physical unclonable function (PUF) is a key enabler to lightweight, low-power and secure authentication of resource-constrained devices in IoT. Nevertheless, current PUF-enabled authentication protocols, with or without the challenge-response pairs (CRPs) of each of its interlocutors stored in the verifier’s side, are incompatible for P2P IoT scenarios due to the security, storage and computing power limitations of IoT devices. To solve this problem, a new lightweight PUF-based mutual authentication and key exchange protocol is proposed. It allows two resource-constrained PUF embedded endpoint devices to authenticate each other directly without the need for local storage of CRPs or any private secrets, and simultaneously establish the session key for secure data exchange without resorting to the public-key algorithm. The proposed protocol is evaluated using the game-based formal security analysis method as well as the automatic security analysis tool ProVerif to corroborate its mutual authenticity, secrecy, and resistance against replay and man-in-the-middle (MITM) attacks. Using two Avnet Ultra96-V2 boards to emulate the two IoT endpoint devices, a physical prototype system is also constructed to demonstrate and validate the feasibility of the proposed secure P2P connection scheme. A comparative analysis shows that the proposed protocol outperforms related protocols in terms of security features, computational complexity as well as communication and storage costs. Ministry of Education (MOE) Submitted/Accepted version This research is supported by the Singapore Ministry of Education AcRF Tier 2 grant No. MOE-T2EP50220- 0003.

With new applications made possible by the fusion of edge computing and artificial intelligence (AI) technologies, the global market capitalization of edge AI has risen tremendously in recent years. Deployment of pre-trained deep neural network (DNN) models on edge computing platforms, however, does not alleviate the fundamental trust assurance issue arising from the lack of interpretability of end-to-end DNN solutions. The most notorious threat of DNNs is the backdoor attack. Most backdoor attacks require a relatively large injection rate (≈ 10%) to achieve a high attack success rate. The trigger patterns are not always stealthy and can be easily detected or removed by backdoor detectors. Moreover, these attacks are only tested on DNN models implemented on general-purpose computing platforms. This paper proposes to use data augmentation for backdoor attacks to increase the stealth, attack success rate, and robustness. Different data augmentation techniques are applied independently on three color channels to embed a composite trigger. The data augmentation strength is tuned based on the Gradient Magnitude Similarity Deviation, which is used to objectively assess the visual imperceptibility of the poisoned samples. A rich set of composite triggers can be created for different dirty labels. The proposed attacks are evaluated on pre-activation ResNet18 trained with CIFAR-10 and GTSRB datasets, and EfficientNet-B0 trained with adapted 10-class ImageNet dataset. A high attack success rate of above 97% with only 1% injection rate is achieved on these DNN models implemented on both general-purpose computing platforms and Intel Neural Compute Stick 2 edge AI device. The accuracy loss of the poisoned DNNs on benign inputs is kept below 0.6%. The proposed attack is also tested to be resilient to state-of-the-art backdoor defense methods. National Research Foundation (NRF) Submitted/Accepted version This research is supported by the National Research Foundation, Singapore, under its National Cybersecurity Research & Development Programme/Cyber-Hardware Forensic & Assurance Evaluation R&D Programme (Award: CHFA-GC1- AW01).

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs. National Research Foundation (NRF) Accepted version This research project is supported by the National Research Foundation, Singapore under its National Cybersecurity R&D (NCR) Research Programme in Assuring Hardware Security by Design in Systems on Chip, SOCure (NRF2018NCR-NCR002- 001), and NTUtive GAP fund (NGF-2017-03-013).

Scan-based side-channel attacks have become a new threat to cryptographic chips. Existing countermeasures require a secret test key to unlock the scan chain before in-field testing is allowed. However, test key disclosure poses tremendous risks to multiple crypto chips that share a common test key. We address this open problem of in-field testing by leveraging physical unclonable function (PUF) to make the derived test key unique to each chip. The PUF’s response is invoked only once and hardened into a one-time programmable pad. The PUF response required by the designer to derive a test key of each crypto chip can only be recovered at the time of locking the scan chains without directly reading it out. The manufacturer can test the chip normally with no test time penalty before the passed chips are locked. The proposed solution is analyzed to be secure against all known scan-based side-channel attacks and the overhead incurred for the added security is negligibly small. Ministry of Education (MOE) Accepted version This research was supported in part by the National Natu- ral Science Foundation of China under Grant 61672182, the Guangdong Natural Science Foundation under Grant 2016A030313662 and the Shenzhen Overseas High-Level Talent Innovation Foundation under Grant KQJSCX20160226202510, and in part by the Singapore Ministry of Education Tier 1 Grant MOE2018-T1-001-131 (RG87/18).

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and inentropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation. Ministry of Education (MOE) Published version This work is supported by grants from the Engineering and Physical Sciences Research Council (EPSRC) (EP/N508664/- CSIT2), the Singapore Ministry of Education AcRF Tier 1 Grant No. 2018-T1-001-131, the National Natural Science Foundation of China (62022041 and 61871216), the Fundamental Research Funds for the Central Universities China (NE2019102) and the Six Talent Peaks Project in Jiangsu Province (2018XYDXX-009).

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory dot-product for neural networks. The proposed architecture allows the NVM operations in both 2T2R and conventional 1T1R configurations. The proposed LiM full adder (LiM-FA) improves the delay, the static power, and the dynamic power by 3.2×, 1.2×, and 1.6×, respectively, compared with state-of-the-art LiM-FAs. Furthermore, based on different optimization techniques and robustness analysis, a lower precharge voltage is set for each mode. This reduces the TCAM search energy and 1T1R ReRAM access energy by 1.6× and 1.14×, respectively, compared with the case without optimizations. Agency for Science, Technology and Research (A*STAR) This work was supported by RIE2020 ASTAR AME IAF-ICP Grant under Grant I1801E0030.

A smart mask integrated with a remote, noncontact multiplexed sensor system, or "Lab-on-Mask"(LOM) is designed for monitoring respiratory diseases, such as the COVID-19. This LOM can monitor the heart rate, blood oxygen saturation, blood pressure, and body temperature associated with symptoms of pneumonia caused by coronaviruses in real time. Because of this remote monitoring system, frontline healthcare staff can minimize the exposure they face from close contact with the patients and reduce the risks of being infected. Agency for Science, Technology and Research (A*STAR) This work was supported by the Agency for Science, Technology and Research (A*STAR) under its AME Programmatic Funding Scheme of Cyber-Physiochemical Interfaces Programme (Project A18A1b0045) and BSEWWT project fund from National Research Foundation Singapore, administrated through the BSEWWT program office (Ref. BSEWWT2017 2 06).

In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolute temperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only 4.38 µm2 (i.e., 1036 F2), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF’s core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 ◦C and 1.2 V. By varying the operating temperature from −50 ◦C to 150 ◦C in a step size of 10 ◦C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV). Ministry of Education (MOE) Accepted version This work was supported by Kongque Technology Innovation Foundation of Shenzhen (KQJSCX20170727101037551), Fundamental Research Foundation of Shenzhen (JCYJ20190808151819049), Singapore Ministry of Education Tier 1 grant MOE2018-T1-001-131 (RG87/18), and Natural Science Founda- tion of Jiangsu Province (BK20191160).

With the increasing prevalent of digital devices and their abuse for digital content creation, forgeries of digital images and video footage are more rampant than ever. Digital forensics is challenged into seeking advanced technologies for forgery content detection and acquisition device identification. Unfortunately, existing solutions that address image tampering problems fail to identify the device that produces the images or footage while techniques that can identify the camera is incapable of locating the tampered content of its captured images. In this paper, a new perceptual data-device hash is proposed to locate maliciously tampered image regions and identify the source camera of the received image data as a non-repudiable attestation in digital forensics. The presented image may have been either tampered or gone through benign content preserving geometric transforms or image processing operations. The proposed image hash is generated by projecting the invariant image features into a physical unclonable function (PUF)-defined Bernoulli random space. The tamper-resistant random PUF response is unique for each camera and can only be generated upon triggered by a challenge, which is provided by the image acquisition timestamp. The proposed hash is evaluated on the modified CASIA database and CMOS image sensor-based PUF simulated using 180 nm TSMC technology. It achieves a high tamper detection rate of 95.42% with the regions of tampered content successfully located, a good authentication performance of above 98.5% against standard content-preserving manipulations, and 96.25% and 90.42%, respectively, for the more challenging geometric transformations of rotation (0 ∼ 360◦) and scaling (scale factor in each dimension: 0.5). It is demonstrated to be able to identify the source camera with 100% accuracy and is secure against attacks on PUF. MOE (Min. of Education, S’pore) Accepted version

This article presents a single-channel voltage-scalable 8-GS/s 8-b time-domain analog-to-digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging asynchronous pipeline successive approximation (APSA), which reduces the quantization period to approximate one-stage time-domain comparator decision time. A co-design methodology of voltage-to-time converter (VTC) and time-to-digital converter (TDC) is proposed to optimize the ADC linearity without increasing the complexity or power consumption, reducing the linearity request of VTC. In addition, concurrent charge redistribution and voltage pull-up is deployed in the VTC, supporting the rail-to-rail input and enabling voltage scalability. The TD-ADC is fabricated in 28-nm CMOS and occupies an active area of 0.011 mm 2 , demonstrating 39.2-dB signal-to-noise-distortion ratio (SNDR) and 56.1-dB spurious-free dynamic range (SFDR) at 0.9 V, 8-GS/s with 85.3-mW power dissipation and 37.6-dB SNDR and 56.3 dB SFDR at 0.7 V, 5.05 GS/s with 23.1-mW power dissipation, achieving 143.1-and 74.3-fJ/conv.-step Nyquist Walden figure of merit (FoM W ), respectively. Ministry of Education (MOE) This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114.

With IT consumerization, access control to remote system by endpoint user and endpoint device is mandatory for security and privacy protection. Existing systems bind an end-user with his/her registered devices but authenticate only the user and device independently. This work presents a novel UDhashing scheme, which is capable of providing a bipartite authentication of both end-user and end-device as a whole, and mutual authentication between the endpoint and the verifier. Non-contact facial biometric is extracted as user identity and physical unclonable function (PUF) is embedded into the device to generate a device “fingerprint”. UDhashing serves as an intermediary to unify the macroscopic human biometric and microscopic silicon entropy source into a single identity. The scheme is demonstrated using measured silicon data of a diode-clamped inverter based strong PUF fabricated in 40nm 1.1V CMOS technology, and the ORL and Ext. Yale B face databases. The experimental results show that the proposed system has good authentication performance with excellent discriminability for different (challenge, user, device) tuples. Besides, the proposed system is analyzed to be resilient to several known attacks. Its reliability and authentication performance can be easily enhanced by low-cost error-correction technique without compromising security. Ministry of Education (MOE) Accepted version This project was supported by the Singapore Ministry of Education MOE Tier 1 grant No. 2018-T1-001-131, RG87/18 (S), and the National Natural Science Foundation of China (61601168).

The attack efficacy of Differential Power Analysis (DPA), a popular side channel evaluation technique for key extraction, is compromised by the false highest Difference Of Means (DOMs) value (‘ghost peaks’) in the DOMs matrix produced in a conventional DPA. The ghost peak is generated by the wrong key guess and always occurs in the conventional DPA when the number of side channel traces is not enough. In this paper, an improved version of the conventional DPA termed as Normalized DPA (NDPA) is proposed to circumvent the ghost peak. With the analysis on the generation of ghost peaks in the conventional DPA, we observed that by normalizing the DOMs matrix, the ghost peaks can be greatly suppressed. We model the proposed NDPA mathematically and show that it performs better than the conventional DPA. We further provide the experimental validations on a set of 200k power simulation traces on AES SBox and 500 EM traces from ASCAD dataset. Based on the attack results of these datasets, our proposed NDPA requires (up to 68%) lesser number of traces to reveal a correct key when compared to the conventional DPA. National Research Foundation (NRF) Accepted version This research project is supported by the National Research Foundation, Singapore under its National Cybersecurity R&D (NCR) Research Programme in Assuring Hardware Security by Design in Systems on Chip, SOCure (NRF2018NCR-NCR002-001)

A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.

The Internet data has reached exa-scale (1018 bytes), which has introduced emerging need to re-examine the state-of-the-art hardware architectures for data-oriented computing. There is an increasing need in the current artificial intelligence and machine learning developments. The traditional pure software-based platform cannot satisfy such an increasing need for data analytics. To analyze such a huge volume of data, we need a scalable hardware platform for both data storage and processing. The main bottleneck is from the well-known memory bottle-neck. As such, one needs to design a novel energy-efficient hardware architecture that is capable to perform the future big-data driven application. There are critical challenges in the traditional semiconductor memory technologies. With the scaling down to nano-scale, many problems appear such as process variation, leakage current and I/O bandwidth limitations. The recent emerging resistive-random-access- memory (RRAM) has shown great potential to be the solution for data-intensive applications. Besides the minimized leakage power due to non-volatility, RRAM in crossbar structure has been exploited as computational elements. As such, both memory and logic components can be realized in a power- and area- efficient manner. More importantly, it can provide a true in-memory logic-memory integration architecture without using I/Os. Therefore, the RRAM based architecture is considered as a potential universal memory for the future big-data applications. In this PhD thesis, we will explore the development of RRAM based logic operations and NVM in-memory architecture, as well as mapping details of various machine learning algorithms on such an architecture. Firstly, for the RRAM based in-memory computing implementation, NVM-SPICE is used for simulation for RRAM based circuits in circuit level. The measurement results of forming, SET and RESET processes are also shown. For the diffusive-type RRAM, a sub-circuit model is used for simulation. A binary RRAM-crossbar for matrix-vector multiplication is developed. Due to the non-uniformity of RRAM device, the proposed binary RRAM-crossbar can perform the computation more accurately compared to traditional RRAM-crossbar in analogue fashion. In addition, three kinds of crossbar structures including passive array, 1T1R and 1S1R are discussed. An RRAM based coupled oscillator network for L2-norm calculation is also shown. A simple oscillator can be built based on the ON-OFF switching of diffusive-RRAM or the forming process of drift-RRAM. When the basic oscillators form a network, it can perform an L2-norm calculation based on the fitted simulation results. Secondly, for the in-memory accelerator, a distributed in-memory computing architecture (XIMA) is developed. Apart from traditional store and load, we define two more commands: start and wait. In addition, all the logic blocks and data blocks are formed in pairs so that the delay of data-processing communication can be minimized. CMOS logic such as instruction queue and decoders are also designed. In addition, 3D CMOSRRAM architecture is investigated. For single-layer 3D architecture, RRAM devices are vias connecting top-layer wordlines and bottom-layer bitlines. All the other CMOS logics are implemented in the bottom layer. For multi-layer 3D architecture, we use two RRAM layers as data buffer and logic implementation, respectively. In addition, TSVs are used to connect different layers. Thirdly, for the data analytics mapping on RRAM based architecture, we have accelerated three machine learning algorithms on XIMA. The learning and inference procedures of single-layer feed-forward neural network (SLFN) have been optimized and partially mapped on the passive binary RRAM-crossbar. In addition, we mapped the binary convolutional neural network (BCNN) on both passive array and 1S1R array with different mapping schemes. Moreover, L2-norm gradient based learning and inference are also implemented on an RRAM network with both crossbar and coupled oscillators. As for 3D CMOS-RRAM architecture, we also mapped the optimized SLFN algorithm. All the operations in learning and inference stages are implemented so that it can achieve the on-line learning. In addition, tensorized neural network (TNN) is mapped on both single-layer and multi-layer accelerators with different mapping scheme. Doctor of Philosophy (EEE)

In the past years, extensive research has been carried out on wireless power transfer (WPT), since it offers customers a convenient charging technique compared to wires which can be inconvenient and allows charging of portable devices in a wide power range. WPT technology has been observed to have some remarkable technological advantages due to its spatial freedom. Owing to modern power electronics technology and high-power semiconductors, WPT technology is highly integrated, and many smart WPT devices have been developed for different applications such as biomedical devices, electric vehicles (EV), and portable consumer electronic devices. A burst in the WPT market for consumer electronics is expected in the coming five years, due to the ubiquitous usage of 3G/4G wireless networks and continually evolving technologies for media and entertainment. WPT systems for consumer devices can be classified into two main types: inductive power transfer (IPT) and magnetic resonant coupling (MRC). The former works at 100-200 kHz, whereas the latter works at 6.78 or 13.56 MHz. The bottleneck of the IPT technology is to design a low cost but high performance WPT system since the IPT mainly targets on the application with less requirement of distance freedom like home appliance or some industrial applications with short charging distance. The main targets of MRC technology is to provide consumers a flexible WPT solution with higher distance freedom. The main concern of this technology is that 1) it is challenging to design high efficiency circuits for MHz application, especially for rectifier; 2) the control of the MRC is challenging since the output power would be effected remarkably by distance, which is known as splitting frequency phenomenon. This research develops circuits and control algorithms for both types of WPT systems. Firstly, a single-stage AC-DC voltage regulator is developed. A noncharging configuration is introduced to regulate the output voltage at a desired level with a pulse width modulation (PWM) control algorithm. In this way, there is no need for the DC-DC stage after the rectifier and additional wireless communication circuit blocks. In addition, a full-active cross-coupled structure is utilized to reduce the power loss of the regulator. Experimental results of the proposed regulator based on a 0.35 µm technology and PCB circuit demonstrate a maximum output power of 15 W and peak efficiency of 92 %. Another contribution of this dissertation is a design of a full active rectifier working at 6.78 MHz. An adaptive time delay (ATD) circuit is used to maximize the conduction interval of the gallium nitride (GaN) switch in order to minimize the power loss due to the forward voltage drop of the diode. The proposed control algorithm also eliminates the reverse leakage current of the rectifier. Except the power devices, all the other circuits have been taped out with a 0.18 µ m CMOS process. The experimental results of the proposed rectifier shows that it can output a maximum output current of 3 A at 5 V with a 6.78-MHz AC input voltage with a peak power efficiency over 90%. The last contribution is a novel control method for a 6.78-MHz MRC system. In this part, detailed analysis of MRC, especially on the relationship between operating frequency, transfer efficiency, output power, and coupling coefficient are presented. Contrary to the traditional research, this research proves that the MRC system is able to work with sufficient output power and efficiency within a wide coupling coefficient range, relaxing the system from the bound of the key coupling coefficient limitation. A hybrid control method with frequency/phaseshift tuning with zero voltage switching (ZVS) Class-D amplifier is proposed to provide the load with a constant output voltage. The testing results shows that it is able to transfer 10 W over a 5 cm with an overall efficiency (end to end) of 71.8 %, and over a 1 cm with an overall efficiency of 73.1%. Doctor of Philosophy (EEE)

Recent progress in integrated circuits (IC) technology and design techniques, especially in ultra-low power circuits domain, has led a rapid growth of fully integrated and portable electronics within internet of things (IoT) smart nodes and wearable sensors system on chip (SoC). IoT applications including biomedical sensors, body area networks and wireless sensors, have taken advantage of such a progress. However, with the increase of people needs, numerous blocks must be integrated within the IoT SoC. Hence, a compact, efficient and self-sustained power management circuit (PMC) with a long life-time design becomes crucial for IoT SoC. Thus, energy scavengers, such as photovoltaic cells (PV), thermos-electric generators (TEG) and electro-static harvesters, become an attractive solution to power the PMC, for self-sustaining and prolonged life time systems. Switched capacitor charge pump (SCCP) along with low drop out (LDO) regulators are an adequate solution for PMC within energy harvesting systems (EHS) for their integrability on-chip, avoiding bulky off-chip inductors, especially for implantable biomedical applications. However, these regulators must be controlled with a maximum power point tracking (MPPT) system to maximize the energy being harvested and to store it efficiently. It should be noted that the MPPT control the regulators whether to maximize the harvested power transfer as per load demand, or to condition the regulator to harvest the maximum available power from the energy harvester. For instance, many MPPT have been developed to track the maximum power point to maximize the tracking efficiency and/or the conversion efficiency.x Several requirements that should be met are wide input voltage handling, wide output load range coverage, output voltage regulation and ultra-low power consumption. The latter one is of a great concern to maximize the EHS overall efficiency and extend its lifetime in case of battery powered PMC. In the first part of this thesis, I propose a novel ultra-low power MPPT technique with a wide tracking range. The proposed technique is an indirect, noninterrupting approach using a novel timing-based algorithm addressing the tracking efficiency. The proposed time-based MPPT technique is self-adaptive and applicable to several types of PVs and TEGs without external reconfiguration or change of passive components. It reduces the power consumption and design complexity. It consists of an ultra-low power digital processing unit to execute the proposed timingbased algorithm along with an ultra-low power window comparator to track the maximum open circuit voltage (Vmpp) without the need to voltage references, perturbation steps and power-hungry voltage or current sensors. In addition, a variable gain is employed using a one-hot barrel shift register to reduce the transient response time in case of an abrupt input voltage change. A test chip was fabricated in 65-nm CMOS technology. The test chip can harvest energy with the input voltage range of 0.4 V to 1.7 V and the step response time of less than 100 ms at the minimum supply voltage of 0.8 V. The tracking efficiency is up to 96.2 % when supplied by a photovoltaic (PV) micro-cell array using an irradiation range of 200 lux to 1000 lux. In the next part of this thesis, a three-dimensional MPPT (3-D MPPT) technique is proposed, addressing the conversion efficiency, for ultra-low power EHS within IoT smart nodes. The proposed MPPT improves the conversion efficiency overxi a wide load range using a novel switch width modulation (SWM) technique. It enhances the conversion efficiency at ultra-light load condition by eliminating the trade-off between the gate driver and conduction loss. The proposed SWM technique modulates the SCCP transistors size in proportion to the load condition, input voltage and the swing voltage applied. The tested chip, fabricated in 65-nm CMOS technology, can harvest from 0.35 V and provides a regulated output voltage at 1 V with peak efficiency of 88% at 200 µW and conversion efficiency > 60% at 100 nW. The last part of this thesis devoted to a fully integrated, low voltage digital lowdropout voltage (DLDO) regulator for ultra-low power applications with a load current aware clock modulation scheme. The proposed DLDO presents a novel clock modulation scheme that enhances the trainset performance without degrading the overall DLDO current efficiency. The proposed clock modulation (CM) increases the clock frequency when the load current changes abruptly eliminating the speedefficiency trade-off using a fixed clock frequency. Thus, it enhances the transient response performance without sacrificing the current efficacy. The proposed DLDO chip is fabricated using 65-nm CMOS technology. It operates at 0.6 V voltage supply with 50mV dropout voltage. It achieves of 99.7% as current efficiency with load current range 10 μA to 200 μA and the quiescent current 0.9 μA. Doctor of Philosophy (EEE)

With the rapid development of system-on-chip integration and continuously scaling-down power supply, nowadays portable battery-powered devices have higher and sharper energy requirements. Switching converters are widely used as voltage regulators in those devices because of its high power-conversion efficiency. Due to the high-speed application and different modes operation requirements, the embedded microprocessors or digital systems operate at a higher frequency and the system need to switch between different modes more frequently. The frequently changing load induces significant undershoot/overshoot variation, which will deteriorate the overall system performance and stability. In this prospective, the fast-transient response becomes one of the key requirements for DC-DC converters in nowadays high-performance applications. Investigation of fast-transient techniques has been conducted to improve the transient response of DC-DC buck converters. A new pumping control scheme called Power-Driving-Tracked-Duration (PDTD) control is proposed to enhance the transient performance in the voltage-mode hysteretic DC-DC converters. It operates only when a large load current change is detected. Comparing with conventional counterparts, it simultaneously accelerates the transient response, reduces the undershoot/overshoot voltage and the effect of multiple undershoots/overshoots during the load current transitions. A theoretical analysis is also conducted to validate the circuit technique. The measured output voltage ripple is about 60mVpp. The obtained undershoot/overshoot settling time is 369ns/335ns in response to a 60-to-300mA/300-to-60mA load current step. The peak efficiency is about 93%. The prototype is fabricated using TSMC 40nm CMOS process as a proof-of-concept. Master of Engineering

Deep neural network (DNN) accelerators overcome the power and memory walls for executing neural-net models locally on edge-computing devices to support sophisticated AI applications. The advocacy of 'model once, run optimized anywhere' paradigm introduces potential new security threat to edge intelligence that is methodologically different from the well-known adversarial examples. Existing adversarial examples modify the input samples presented to an AI application either digitally or physically to cause a misclassification. Nevertheless, these input-based perturbations are not robust or surreptitious on multi-view target. To generate a good adversarial example for misclassifying a real-world target of variational viewing angle, lighting and distance, a decent number of target's samples are required to extract the rare anomalies that can cross the decision boundary. The feasible perturbations are substantial and visually perceptible. In this paper, we propose a new glitch injection attack on DNN accelerator that is capable of misclassifying a target under variational viewpoints. The glitches injected into the computation clock signal induce transitory but disruptive errors in the intermediate results of the multiply-and-accumulate (MAC) operations. The attack pattern for each target of interest consists of sparse instantaneous glitches, which can be derived from just one sample of the target. Two modes of attack patterns are derived, and their effectiveness are demonstrated on four representative ImageNet models implemented on the Deep-learning Processing Unit (DPU) of FPGA edge and its DNN development toolchain. The attack success rates are evaluated on 118 objects in 61 diverse sensing conditions, including 25 viewing angles (-60° to 60°), 24 illumination directions and 12 color temperatures. In the covert mode, the success rates of our attack exceed existing stealthy adversarial examples by more than 16.3%, with only two glitches injected into ten thousands to a million cycles for one complete inference. In the robust mode, the attack success rates on all four DNNs are more than 96.2% with an average glitch intensity of 1.4% and a maximum glitch intensity of 10.2%. National Research Foundation (NRF) Accepted version This research is supported by the National Research Foundation, Singapore, under its National Cybersecurity Research & Development Programme/Cyber- Hardware Forensic & Assurance Evaluation R&D Programme (Award: CHFA-GC1AW01).

Using a quadrature XOR-gate (QXOR) reduces the second order harmonic term at the output, making it suitable to be used as a phase/frequency detector in high-frequency phase-locked loops. This paper introduces a 320 GHz PLL employing QXOR to cancel the reference spur, suppress in-band noise, and also reduces the power consumption of the frequency tracking loop (FTL). The beat frequency of FTL enables the lock detector (LD) to search the right band for VCO operation. The proposed PLL was implemented in IHP 0.13 μm SiGe BiCMOS process. Measured results show that the PLL achieves a locking range from 307.45 GHz to 321.28 GHz, while consuming 372 mW DC power, with −113.7 dBc/Hz phase noise at 1 MHz offset measured at 40.96 GHz. This leads to an integrated RMS jitter (1k−30MHz) of 72 fs. The measured phase noise at 311.6 GHz is –90 dBc/Hz at 1 MHz offset, with a total division ratio of 512. The measured maximum probed output power is –3.3 dBm. The PLL occupies a 1.4 mm2 area. Ministry of Education (MOE) Accepted version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 (MOE2019-T2-1-114).

A simple yet effective approach for variable-gain amplifier (VGA) design with accurate dB-linear characteristic is presented. In order to extend the bandwidth of the designed VGA with a minimized footprint, an inductorless-based approach is adopted. Moreover, a unique approach that exploits a self-compensated transistor to compensate dB-linear gain error is proposed. Consequently, the overall VGA has an accurate dB-linear inherent characteristic without using any additional exponential generator for gain control. To prove the concept, the designed VGA is fabricated in a standard 65 nm CMOS technology. The measured results show that the voltage gain of the designed VGA can be controlled from -19 dB to 21 dB with a gain error less than 1 dB. Meanwhile, more than 4 GHz of bandwidth can be achieved for the entire gain range. The power consumption of the VGA, excluding the output buffer, is 3.9 mW. The core circuit of this design only occupies an area of 0.012 mm². National Research Foundation (NRF) Accepted version This work was conducted within the DeltaNTU Corporate Lab for Cyber-Physical Systems with funding support from Delta Electronics Inc. and the National Research Foundation (NRF) Singapore under the Corp Lab@University Scheme.

Silicon physical unclonable function (PUF) has emerged as a promising spoof-proof solution for low-cost device authentication. Due to practical constraints in preventing phishing through public network or insecure communication channels, simple PUF-based authentication protocol with unrestricted queries and transparent responses is vulnerable to modeling and replay attacks. Although PUF itself is lightweight, the ancillary cryptographic primitives required to support secure handshaking in classical PUF-based authentication protocol is not necessarily so. In this paper, we present a modeling attack resistant PUFbased mutual authentication scheme to mitigate the practical limitations in applications where a resource-rich server authenticates a device with no strong restriction imposed on the type of PUF design or any additional protection on the binary channel used for the authentication. Our scheme uses an active deception protocol to prevent machine learning (ML) attacks on a device with a monolithic integration of a genuine Strong PUF (SPUF), a fake PUF, a pseudo random number generator (PRNG), a register, a binary counter, a comparator and a simple controller. The hardware encapsulation makes collection of challenge response pairs (CRPs) easy for model building during enrollment but prohibitively time-consuming upon device deployment through the same interface. A genuine server can perform a mutual authentication with the device using a combined fresh challenge contributed by both the server and the device. The message exchanged in clear cannot be manipulated by the adversary to derive unused authentic CRPs. The adversary will have to either wait for an impractically long time to collect enough real CRPs by directly querying the device or the ML model derived from the collected CRPs will be poisoned to expose the imposer when it is used to perform a spoofing attack. The false PUF multiplexing is fortified against prediction of waiting time by doubling the time penalty for every unsuccessful guess. Our implementation results on field programmable gate array (FPGA) device and security analysis have corroborated the low hardware overheads and attack resistance of the proposed deception protocol. Ministry of Education (MOE) Accepted version This work was supported in part by the Singapore MOE Tier 1 under Grant MOE2018-T1-001-131 RG87/18(S); in part by the Engineering and Physical Sciences Research Council (EPSRC) under Grant EP/N508664/-CSIT2; and in part by the National Natural Science Foundation of China under Grant 62022041 and Grant 61771239.

The convergence of edge computing and deep learning empowers endpoint hardwares or edge devices to perform inferences locally with the help of deep neural network (DNN) accelerator. This trend of edge intelligence invites new attack vectors, which are methodologically different from the well-known software oriented deep learning attacks like the input of adversarial examples. Current studies of threats on DNN hardware focus mainly on model parameters interpolation. Such kind of manipulation is not stealthy as it will leave non-erasable traces or create conspicuous output patterns. In this paper, we present and investigate an imperceptible misclassification attack on DNN hardware by introducing infrequent instantaneous glitches into the clock signal. Comparing with falsifying model parameters by permanent faults, corruption of targeted intermediate results of convolution layer(s) by disrupting associated computations intermittently leaves no trace. We demonstrated our attack on nine state-of-the-art ImageNet models running on Xilinx FPGA based deep learning accelerator. With no knowledge about the models, our attack can achieve over 98% misclassification on 8 out of 9 models with only 10% glitches launched into the computation clock cycles. Given the model details and inputs, all the test images applied to ResNet50 can be successfully misclassified with no more than 1.7% glitch injection. Ministry of Education (MOE) Accepted version This research is supported by Singapore Ministry of Education AcRF Tier 1 Grant No. 2018-T1-001-131.

This article presents a closed-loop transmitter for wireless power transfer with automatic resonance frequency tracking to maintain high power transfer efficiency in the over-coupled region. The transmitter consists of a source oscillator, power amplifier (PA), PA driver, matching network, and feedback circuitry. By injecting the resonant output of coupled antenna coils into a source oscillator to form a positive feedback loop, the source oscillator is injection-locked and the closed-loop transmitter functions as a power oscillator with the oscillation frequency determined by the resonance of the coupled coils. The proposed resonant frequency tracking minimizes the change in the input impedance presented to the PA, and hence mitigates mismatch that causes a sharp drop in the PA efficiency of conventional transmitters. Implemented in 0.13 μm Bipolar-CMOS-DMOS (BCD) technology, the prototype maintains PA efficiency above 60% even at highly over-coupled spacings (10 mm), which is significantly below the critical coupling spacing (40 mm). Compared to a transmitter without feedback (i.e., running in open loop), the transfer efficiency at a coupling distance of 10 mm is improved by 6.6 times and the charging range with power transfer efficiency over 50% is also doubled. Ministry of Education (MOE) Nanyang Technological University Submitted/Accepted version This was supported in part by Ministry of Education, Singapore, under Grant AcRF TIER 1- 2018- T1-001-120 (RG 86/18) and in part by Nanyang Technological University under Grant M4082082.040.

This paper presents a fast and effective polarization image demosaicking algorithm, which explores inter-channel dependency of Stokes parameters for the minimization of residual aliasing artifacts after cubic spline interpolation. A guided filtering approach is used for denoising. An optimization based on the confidence level of the aforementioned guided filtering, the correlations between the demosaicked image and input, as well as the total intensity, angle and degree of linear polarization, is constructed and solved with Newton’s method. Experimental results demonstrate that the proposed algorithm can surpass the existing methods in terms of both objective root mean squared error and structural similarity index by at least 36.0% and 3.4%, respectively, and by close visual inspection of the clarity of objects in the angle and degree of linear polarization images. The proposed algorithm consists of only convolutions and elementwise operations, making it fast and parallelizable for efficient GPU acceleration. An image of size 512×612×4 can be processed within 10 s on i7-6700k CPU, and gains further 5 times speedup with M4000M GPU. Ministry of Education (MOE) Accepted version This work was supported in part by the Nanjing University of Aeronautics and Astronautics, Nanjing, China, under Grant 56Y AH18043 and Grant PAC19009 and in part by the Singapore Ministry of Education AcRF Tier 1 under Grant MOE2018-T1- 001-131, RG87/18-(S).

Despite superior accuracy on most vision recognition tasks, deep neural networks are susceptible to adversarial examples. Recent studies show that adding carefully crafted small perturbations on input layer can mislead a classifier into arbitrary categories. However, most adversarial attack algorithms only concentrate on the inputs of the model, effect of tampering internal nodes is seldom studied. Adversarial attack, if extends to deployed hardware system, can perturb or alter intermediate data during real time processing. To investigate the vulnerability implication of deep neural network hardware under potential adversarial attacks, we comprehensively evaluate 10 popular DNN models by injecting noise into each layer of these models. Our experimental results indicate that more accurate networks are more prone to disturbance of selective internal layers. For traditional convolutional network structures (AlexNet and VGG family), the last convolution layer is most assailable. For state-of-the-art architectures (Inception, ResNet and DenseNet families), as little as 0.1\% or one element per channel of perturbations can subvert the original predictions, and over 65\% of computational layers suffer from this vulnerability. Our findings reveal that optimization of accuracy, model size and computational efficiency can unconsciously sacrifice the robustness of deep learning system. MOE (Min. of Education, S’pore) Accepted version

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator (TRNG), in field programmable gate array (FPGA) are crucial replacement of the conventional decryption key stored in batterybacked random-access memory (RAM) or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA, is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (PicoPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single C. Gu*, N. Hanley, J. Miskelly and M. O’Neill Centre for Secure Information Technologies (CSIT) Queen’s University Belfast, Belfast, U.K. E-mail: {cgu01, n.hanley, jmiskelly}@qub.ac.uk E-mail: m.oneill@ecit.qub.ac.uk C. H. Chang School of Electrical and Electronic Engineering Nanyang Technological University, Singapore E-mail: echchang@ntu.edu.sg W. Liu* College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics Nanjing, China E-mail: liuweiqiang@nuaa.edu.cn * corresponding authors slice disorder-based security entities have been investigated and compared on 28nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bitaliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the minentropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF (RO PUF) and some existing memory based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design is made publicly available to enable the research community to use them for benchmarking and/or validation.

In recent years, the demand for the battery-powered devices has been increasing rapidly. At the same time, the requirements for the audio power amplifier (APA) also extend to hi-fi quality music playback. In order to achieve high run time per charge for the portable devices, the quiescent power consumption of APA should be made as low as possible. As such, the quiescent power consumption, harmonic distortion and dynamic range become the most significant performance parameters in the design of high-performance headphone amplifiers. Compared to the class-D amplifier, class AB amplifier has the key advantages of high PSRR, low THD+N, no switching noise and no electro-magnetic interference. In this thesis, a low-quiescent class-AB headphone driver, which is powered by dual supplies of ±1V, is presented and analyzed. Due to the small resistive load of APA, the mismatch-induced quiescent current caused by the input-referred offset voltage becomes a significant effect on the quiescent power consumption. It is evident that the mismatch-induced quiescent current of APA will be substantially increased with the increase of amplifier offset. A new balanced offset compensation current approach is presented. Through the aid of digitally-assisted calibration design, the input-referred offset can be substantially reduced while avoiding the unnecessary increase of quiescent power. Since the compensation current is injected into the low impedance nodes of the front-end gain stage, there is no significant degradation in terms of DC gain and power supply rejection ratio (PSRR) of the amplifier. This has demonstrated the robustness of calibration circuit. An improved compensation technique called NMCFNR2, which is the Type-II implementation of nested Miller compensation with feedforward and nulling resistor (NMCFNR) amplifier, is proposed. It offers the technical advantages of simplicity as well as low-quiescent operation. Besides, the modified frequency compensation permits the APA to drive the worst-case load of 16Ω//2nF whilst sustaining good stability and offering good and balanced performance metrics. Together with the channel-length modulation (CLM) reduced class-AB bias generation circuit dedicated to the push-pull output stage, the auto-calibrated APA will reduce the input-referred offset of amplifier down to about 85µV while the total quiescent power is only 0.4mW and the GBW is of about 1.78 MHz. The APA can deliver a peak power of 35mW (1.5Vpp swing) to the worse case load of (16Ω//2nF) with -89dB THD+N and 93.5dB SNR. The extensive measurement results have suggested that the proposed amplifier has achieved the best Figure-of-Merit FOM1= (Peak load power/Quiescent power) and the best FOM2= [Peak load power/Quiescent power*(THD+N)%] when compared with other representative state-of-the-art works. MASTER OF ENGINEERING (EEE)

The analog-to-digital converter (ADC) is one of the key building blocks in digital communication systems. In modern receiver designs, ADCs are usually fabricated on the same die with the digital baseband signal processing block for the dual-chip solution. This implementation takes into considerations of cost, flexibility and packaging. The combination of analog circuits and digital circuits in one die poses numerous challenges in ADC design due to the coupling of digital noise to analog circuits. DOCTOR OF PHILOSOPHY (EEE)

Printed circuit board (PCB) is one of the crucial parts of electronic packaging. It is mounted with a large number of high-speed electronic devices and serves as a platform for numerous interconnections amongst these devices. With the trend of increasing operating frequency, PCB layouts of high-speed digital circuits become important for the circuit designers. Without proper PCB layout consideration at the design stage, electromagnetic interference (EMI) and signal integrity (SI) issues will surface and affect the functionality of the digital circuit. To allow an evaluation of PCB layout to meet EMI and SI requirements at the design stage, accurate and efficient simulating tool for printed circuit interconnects is necessary. For high-speed operating environment in the GHz range, lumped circuit modeling of the interconnecting traces on PCB is no longer accurate. Full-wave electromagnetic modeling of PCB provides excellent simulation results accurately. Nearly all full-wave electromagnetic simulation tools rely on solving Maxwell’s equations using numerical method. It is also well known that modeling large printed circuit structure based on numerical method can be computational prohibitive due to the long computation time to construct the large matrix resulting from numerical method. One of the popular numerical methods for electromagnetic modeling of PCB is the Method of Moments (MoM), which provides the numerical solution of the Maxwell’s equations using the integral formulation. To improve the computational efficiency of MoM based numerical method, efficient and accurate integration of the Green’s function is essential. In this thesis, an in-depth study and analysis on the accurate and efficient integration of Green's function is carried out. By expanding the Green’s function into the Taylor’s series, closed form expression of the integration of the Taylor’s series is developed, which reduces the solution time of MoM method significantly. The analytical expression for the integration of the Green’s function also makes the solution highly accurate. DOCTOR OF PHILOSOPHY (EEE)

With the increasing demand for low cost and high integration of wireless transceiver building blocks, the low-power performance is a great concern for radio-frequency integrated circuit (RFIC) designers. Intensive effort has been made to develop RF integrated circuits and systems in the gigahertz range using the low-cost CMOS process. The commonly used frequency synthesizer based on the phase-locked loop (PLL) is an important building block of the transceiver. The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a major and critical block of a wireless transceiver because it operates at high frequency and consumes a very large portion of the total power consumption in the transceiver. The performance in power consumption and channel selection of frequency synthesizer are limited by the two most important building blocks, namely the voltage-controlled oscillator (VCO) and the high frequency divider. The objective of this research work is to design the critical blocks for the frequency synthesizer with low power consumption. In this thesis, we have carried a detailed analysis on the speed and power consumption of the digital dividers and developed low power prescalers based on the dynamic logic. A CMOS fully programmable 1 MHz resolution divider for Zigbee and IEEE 802.15.4 applications is implemented based on pulse-swallow topology which uses the proposed ultra-low power 2/3 prescaler, low power 47/48 prescaler and a reloadable D flip-flop for the counters. A detailed design of wide-band 2/3 prescaler based on dynamic logic is presented which is suitable for IEEE 802.11 a/b/g applications and also verified in the design of fully programmable Multi-band divider which provides flexible resolution. DOCTOR OF PHILOSOPHY (EEE)

Pre-delay reconstruction sigma-delta beamformer (SDBF) was proposed in recent years to achieve a higher level of integration in ultrasound imaging systems. The high-order reconstruction filter used in each channel of SDBF makes the beamformer highly complex. The beamformer can be simplified by reconstructing the signal only after the delay-and-sum process. It requires only one reconstruction filter for the entire beamformer. However, this post-delay reconstruction-based beamformer degrades the image quality when dynamic focusing is performed. This thesis studied the cause of the dynamic focusing artifact problem suffered by the sigma-delta beamformer. It was found that the degree of the problem is related to the pre-delay quantization noise that is present in the signal. Hence, similar performance to the conventional pre-delay reconstruction SDBF can be achieved by simply employing a simple pre-delay filter, as long as the pre-delay filter provides the required pre-delay signal-to-quantization noise ratio (SQNR). Based on this finding, a cascaded reconstruction beamformer was developed that utilizes a boxcar filter as the pre-delay filter in each channel to achieve the required pre-delay SQNR value. Simulations using real phantom data demonstrated that the proposed cascaded reconstruction beamforming method can achieve a contrast resolution comparable to that of the pre-delay reconstruction beamforming method. In addition, the savings on hardware and power can be as much as 85% and 68% respectively, as compared to the pre-delay reconstruction SDBF. DOCTOR OF PHILOSOPHY (EEE)

With the fast growing electronic portable devices, power management becomes an important area in electronic industry to reduce the power consumption so as to extend the battery life of these devices. Low dropout (LDO) regulator is widely used in power management IC due to its simple structure, low noise and fast speed characteristics. As the technology continues scaling down to deep submicron, the digital circuits display less immunity to Process, Supply voltage, and Temperature (PVT) variations. Therefore, power management technique with PVT compensation becomes another important design approach. This work focuses on the design techniques which include process variation sensing circuit (VTH sensor), wide load capacitance (CL) range with fast speed LDO regulators and digital system supply with PVT compensation capability using LDO regulator.First, the VTH sensor circuit can generate the VTH of a single MOSFET at 0 K (VTH0). VTH0 is temperature and supply invariant but process dependent. The VTH sensor can be utilized to sense the VTH variation of the devices, hence providing the process information. Based on a Brokaw structure with the addition of the proposed current-mode second-order temperature compensation network, this improves the Temperature Coefficient (T.C.), the VTH sensor. Second, a DSMFC technique is proposed in a Flipped Voltage Follower (FVF) LDO regulator architecture. By adding an extra Miller compensation stage, the dominant pole of the feedback system can be pushed to lower frequency whilst the non-dominant pole(s) can be pushed to higher frequency. This extends the CL driving range without sacrificing circuit complexity and quiescent power consumption. Third, a novel Weighted Current Feedback (WCF) technique is proposed in a multi-gain stage LDO regulator architecture. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. As a result, a good optimization of stability, speed and accuracy can be achieved in the context of wide CL range. Finally, a PVT Compensated Supply (PVTCS) for driving point-of-load digital system is designed. By adding a weighted combination of the VTH drift of the PMOS (ΔVTHP) and NMOS (ΔVTHN) diodes onto the reference voltage of a high speed WCF LDO regulator, the supply voltage of the digital circuits is adjusted adaptively. This can reduce the speed deviations of the digital circuits under PVT variations. With the low T.C. VTH sensor circuit to sense the process information, the two wide CL range LDO regulators to drive the digital circuits and the PVTCS to compensate the PVT variations of the digital systems, the works are useful for fully on-chip power management circuits with PVT compensation. DOCTOR OF PHILOSOPHY (EEE)

The analysis of big-data at exa-scale (1018 bytes or flops) has called for an urgent need to re-examine the existing hardware platform that can support intensive data-oriented computing. A big-data-driven application requires huge bandwidth and yet able to ensure low-power density. For example, web-searching application involves crawling, comparing, ranking, and paging of billions of web-pages with extensive memory access. The existing memory technologies have critical challenges of scaling at nano-scale due to process variation, leakage current and I/O access limitations. Recently, the emerging non-volatile memory (NVM) technologies such as resistive-RAM (ReRAM), spin-transfer torque RAM (STT-RAM), domain-wall nanowire racetrack memory etc., have all shown significantly reduced standby power and increased integration density, not forgetting the close-to DRAM/SRAM access speed. Therefore, they are considered as promising candidates of universal memory for future big-data applications. The primary challenge to validate a hybrid design with both CMOS and nonvolatile devices is the lack of design platform that can validate the large-scale NVM circuit and system design accurately and efficiently. In addition, due to the use of non-electrical states of emerging NVM devices, new cells structures and their agreeing circuits for both read and write operations are needed to harness non-volatile memory with unique operations. For example, the transistor-free crossbar array that associates with NVM is different from conventional access transistor based memory structure. What is more, leveraging the NVM for computing, one also needs to examine the potential logic-in-memory computing architecture with significantly improved bandwidth and reduced power. In order to tackle above challenges ranging from device to system levels, this PhD thesis has explored the development of NVM design platform to support designs of non-volatile memories, readout and logic circuit designs, as well as the in-memory computing architecture. For the NVM design platform, the target is to perform accurate yet efficient circuit level simulation. The previous approaches either ignore dynamic effect without considering non-volatile states for dynamic behavior, or need equivalent circuits with high complexity to curve-fit non-linearity of those devices. We proposed a SPICE simulator named NVM-SPICE. This tool takes advantages of its new modified nodal analysis (MNA) framework, which can effectively support the non-electrical state variables of emerging non-volatile devices, such as ReRAM and spintronics devices. Due to the physics based modeling approach, NVM-SPICE is able to perform hybrid NVM/CMOS circuits efficiently and accurately. Compared to the equivalent circuit model based approach, the NVM-SPICE simulator exhibits more than 117x faster simulation speed for spintronics category devices and 40x faster speed for RRAM category devices. For NVM in-memory architecture, both memory elements and logic elements are implemented by emerging spintronics devices, which leads to a system purely composed of non-volatile devices. The detailed non-volatile memory and logic circuits are explored within the NVM-SPICE platform. In addition, logic is built inside the memory so that the I/O workload can be alleviated. Applications such as data retention, encryption, machine learning that play critical roles for big-data computing are explored within the non-volatile in-memory architecture. The evaluation results show that the purely non-volatile memory based platforms with in-memory architecture greatly contribute to power efficiency and throughput improvement for big-data oriented applications, and thus are potential candidates to be next generation information and communication technology. DOCTOR OF PHILOSOPHY (EEE)

Electromigration (EM) occurs in the form of void formation because of mass transport, reducing the electrical reliability of interconnects. The aggressive shrinkage of interconnects while maintaining at high current capability and reliability emerges EM to be a serious reliability issue, especially with the introduction of Cu and low-k dielectric material in the backend integrated circuits. Reservoir region can contribute better EM reliability of interconnects. However, the effectiveness of the reservoir effect in improving EM reliability as a function of line width has not been studied. In this work, experimental studies on the reservoir effect of EM reliability are performed for the Cu/low-k dual-damascene interconnects with varied reservoir lengths in both narrow and wide metal lines. Finite element simulation is applied to assist us in understanding the mechanism of reservoir effect effectiveness. MASTER OF ENGINEERING (EEE)

ΣΔ technique has always been the popular choice for designing high resolution data converters due to the advantage of oversampling and noise shaping. In recent years, continuous time implementation of ΣΔ modulator is attracting more and more research attention for its superior potential to realize low power low voltage and/or high speed design. CT ΣΔ modulator relaxes amplifier‘s unity gain bandwidth requirements which greatly improves its achievable conversion speed. It also has the advantage of implicit anti-aliasing feature. In this research, various design trade-offs and implementation issues have been introduced and discussed. Special focus has been put on the issue of clock jitter which is considered to be the major obstacle for CT ΣΔ modulator to be widely implemented. In this research, a special pulse shaping technique which is called fixed length return-to-zero method was proposed. Simulation shows that it almost achieves the best performance any pulse shaping method can achieve. It not only greatly improves CT modulator‘s jitter performance, but also exerts very little adverse effects such as increased power consumption, circuit overhead, and increased loop delay. For the purposed of verifying various design concepts developed in this research, a 4th order 1-bit prototype modulator integrated in 0.18 μm CMOS technology has been developed. Simulation shows it is able to achieve 85 dB SNDR for 25 kHz input signal range. And the FOM it achieves is 0.22pJ/conversion. The total chip occupies an area of 1.725mm2. MASTER OF ENGINEERING (EEE)

The explosive growth of the internet demand high-speed data transmission due to the multimedia and telecommunication. To break the existing speed bottleneck with the traditional broadband solutions such as Digital Subscriber Line (DSL) and Community Antenna Television (CATV), Fiber-To-The-Home (FTTH) using optical fiber has been developed as a feasible solution for the Local Area Network (LAN). A popular implementation of the FTTH is the Ethernet Passive Optical Network (EPON) system. Two versions of the circuit are designed to operate with 2.5 Gbps data for the burst mode optical receiver inside the Optical Line Terminal (OLT) in the EPON system. The second version of the circuit is an improved version of the first with an added automatic gain control block to increase the dynamic range. The key idea in the two designs is to generate an internal reset signal based on the magnitude of the input signal in a feedforward configuration. DOCTOR OF PHILOSOPHY (EEE)

213 p. Fully integrated frequency synthesizers have been widely adopted for the wireless communication, data communication and optical communication systems to produce precise local oscillator (LO) signals for the channel selection. A frequency synthesizer is required to have a low phase noise in order to prevent the unwanted signals mixing with the interferences. A major challenge in the design of a fully integrated frequency synthesizer is the design of the voltage controlled oscillator (VCO) that affects the noise performance and power consumption of a synthesizer directly. The phase noise of the VCO is one of the most critical parameters for the quality and reliability of the information transfer. The objective of this project is to design high performance LC VCOs for integrated frequency synthesizers. DOCTOR OF PHILOSOPHY (EEE)

In recent years, there is an increasing demand for portable, wearable or implantable biomedical devices. These devices generally require extremely long battery life-time which in turn demands extremely low-power band-pass filters, low-noise amplifiers and low-power ADC. SAR ADC is typically adopted in these devices because of its higher power efficiency compared to other ADC architectures (e.g., flash ADC, pipeline ADC). Nevertheless, a big proportion of energy is still consumed by the conventional SAR ADC. Hence, extensive research is still required to further lower the power consumption. Meanwhile, many biomedical signals vary slightly within a small range for a large portion of time. Incorporating this signal characteristic into the design, a bypass window technique that can increase the power efficiency of the SAR ADC in biomedical signal acquisition is proposed here. This technique is based on the idea that when the input signal is within a predefined range, several conversion steps for the first few significant bits are bypassed, i.e., fewer switching instances happen in the capacitive DAC and hence less power is consumed during the switching sequence. Besides, the design has a 2-stage low-power dynamic comparator and a TSPC DFF constructed phase generator, which helps to lower the overall power consumption further for our SAR ADC. In the current project, the SAR ADC is designed and implemented in GLOBALFOUNDARIES 40nm CMOS process. The simulation results show that with sampling frequency from 0 to 2MHZ, this ADC can achieve a SNDR of 61.55dB and ENOB of 9.93bits. It can reduce 74% of the power dissipation if the bypass window function is triggered. MASTER OF ENGINEERING (EEE)

This report aims to provide a comprehensive review as well as the design of the various high frequency circuits found in almost all the transceivers in the market today. Wireless communication has become a natural part of everyone’s life, its presence can be seen all around. The high frequency circuits include low noise amplifiers (LNA), mixers and pre-amplifiers (PA). In every receiver system, the LNA is the first block placed in the receive path, therefore its performance is critical in the exact operation of the receiver. The primary role of the LNA is to amplify the weak Radio Frequency (RF) signals, having suffered propagation loss after transmission through a medium, while minimizing its noise contribution to the overall system. Gain and noise figure are well correlated, higher gain would produce lower noise figure. Correspondingly, to achieve high gain, power consumption is increased. For mobile wireless devices, this would cause a severe drain on battery life. Therefore a novel LNA, operating in the subthreshold region is introduced to alleviate this issue. Most modulators and demodulators are not able to achieve the high sampling rate required at RF frequencies. Thus, mixers circuits are needed to convert the modulated signals with a carrier frequency to the desired frequency. In the case of a transmitter system, the mixer is used to up convert the modulated immediate frequency (IF) into RF signal for transmission. Due to modulation scheme adopted and high bandwidth requirements of certain wireless applications, a wideband and high linearity mixer is needed to fulfill these functions. Lastly, a transmitter would need to drive an off chip load, usually in the form of an antenna. A PA is usually employed to accomplish the task. By incorporating a power amplifier on-chip several considerations need to be addressed, a power amplifier have high gain resulting in a huge signal swings. These signals tend to find their way to other frequency sensitive circuits such as oscillators, through certain feedback paths or substrate coupling. This effect is normally known as ‘injection pulling’. Proper shielding or isolation is therefore crucial for the proper operation of the entire transceiver system. MASTER OF ENGINEERING (EEE)

173 p. The ultra-wideband (UWB) technology has unique features over a wide range of applications. Comparing with traditional narrowband wireless technologies, UWB technology employs ultra-wide bandwidth and permits high data-rate and very low power transmissions. Since 2003, UWB technology has been undergoing rapid development in both academia and industry. An UWB front-end has to accommodate design challenges over exceptional wide bandwidth, and is of essential importance for overall transceiver system. DOCTOR OF PHILOSOPHY (EEE)

Oscillators are an integral part of many electronic systems. With rapid development in the area of Radio Frequency (RF) and wireless communication, the interest in oscillator which generates Local Oscillator (LO) signal has grown rapidly in the last few years. The LO signal is required to down-convert the RF signal to a lower Intermediate Frequency (IF) signal, or vice versa. For typical RF application, LC Voltage-Controlled Oscillator (VCO) is used. It is essential to tune the VCO for an optimized performance due to two reasons. Firstly, the phase noise of the VCO has great effect on the selectivity of the receiver. Secondly, VCO is one of the most power hungry blocks of the transceiver. Hence the power consumption of the transceiver can be reduced significantly by optimizing that of the VCO. Moreover, for transceivers that implement quadrature modulation/demodulation scheme, the phase error and amplitude error of the LO signal can affect the function of the overall performance significantly. With the development and popularity of Wireless Local Area Network (WLAN) and Personal Area Networks (PANs) which operates in the Industrial, Scientific and Medical (ISM) band, it is essential to design VCO with optimized performance for ISM band application. In this thesis, the aim is to explore the VCO's tuning method, both differential and quadrature, to optimize the overall performance. Firstly, a fully integrated hybrid type Automatic Amplitude Calibration (AAC) VCO has been designed and fabricated in 0.18 µm CMOS technology. The operation of the whole loop and the state-dependent nature is analyzed followed by the analysis of important blocks. Based on these analyses, a quantitative transient analysis for the whole loop is performed. A systematic design procedure is proposed according to the relationship explored in the quantitative transient analysis. Secondly, in order to satisfy the need for quadratuer signal generation with good phase noise and phase error performance, a novel in-phase coupling scheme is proposed. The principle of this in-phase coupling scheme is analyzed first, followed by the analysis for possible sources of phase error. Based on this analysis, two novel schemes for phase error tuning are proposed. DOCTOR OF PHILOSOPHY (EEE)

The rapid development of fast digital signal processors implemented in Complementary metal-oxide-semiconductor (CMOS) very-large-scale integration (VLSI) technology has dramatically increased the demand for high speed and high resolution analog-to-digital converters (ADCs). These ADCs can be integrated in the fabrication technologies and optimized for digital circuit and systems. As the scaling of the VLSI technology also severely constrains the available dynamic range for the interface of the analog and digital signals, the ADCs are the bottleneck in most of the mixed-signal designs. One of the ADC architectures, delta-sigma oversampling ADCs realize an optimum tradeoff between circuit complexity, cost, and power dissipation. High accuracy is achieved with low precision analog components. MASTER OF ENGINEERING (EEE)

The growing portable and battery powered devices have driven the power management circuits to consume as low power as possible so as to prolong the operation life of the devices. Low-dropout (LDO) regulators are important building blocks in power management unit which provides majority or all power sources in a system chip. This work focuses on the circuit design techniques for high-performance regulators for on-chip applications. This thesis presents (i) a new frequency compensation technique for multistage amplifier, (ii) two types of composite power transistor, (iii) a new ultra-low quiescent current regulator architecture and (iv) a new low-impedance loading network circuit design technique for LDO regulator applications. For frequency compensation, the design objectives are to address power-bandwidth-efficiency as well as area-efficiency at a large capacitive load. Turning to the LDO regulator designs, the focuses are to address low quiescent current consumption, low voltage operation, good stability and current efficiency at light loads. A cross feedforward cascode compensation technique is proposed for a three-stage amplifier design. Implemented in 65 nm CMOS technology, the amplifier only consumes a quiescent current of 17 μA at a 1.2 V supply and occupies an active area of 0.0088 mm2. In addition, when driving a 500 pF capacitive load, it achieves a unity-gain bandwidth of 2 MHz with a phase margin of 52°. The proposed amplifier is stabilized by a small compensation capacitor of only 1.15 pF. In view of application as an error amplifier in LDO regulator design, it is particularly useful for driving a power transistor with significant large input capacitance. In another contribution, two types of composite power transistor based regulator are proposed. Due to employment of shunt feedback resistor to reduce impedance in the composite power transistor, the stability criterion is relaxed whereas on-chip compensation capacitor can be reduced to only few pF level. For the first output-capacitorless LDO (OCL-LDO) regulator with push-pull composite power transistor, it can operate at a minimum supply of 0.75 V and supply a maximum load current of 50 mA while consuming only 12.15 μW. It is fabricated in 65 nm CMOS technology and occupies an active area of 0.0096 mm2. The measured output change is 103 mV when load current is switched from 0 to 50 mA in 100 ns at a 100 pF capacitive load. For the second output-capacitor LDO (OC-LDO) regulator with dynamic-biased composite power transistor, it is capable to provide a maximum current of 450 mA from a 1.2 V supply and dissipates only 4.7 μA of quiescent current at zero load current. It is realized and simulated in 0.18 μm CMOS technology. With an output capacitor of 4.7 μF, the simulated output change is 64.62 mV when the load current is changed from 0 to 450 mA in 10 ns. It has shown that both LDO regulators greatly enhance the transient responses with respect to conventional counterparts. Further contribution deals with a new architecture employing adaptive power transistors circuit technique for ultra-low quiescent current OCL-LDO regulator. Depending on the load current, the OCL-LDO regulator transforms itself to a two or three stage configuration automatically. Implemented in 65 nm CMOS process technology, the proposed regulator consumes a quiescent current of 0.9 μA at zero load current. It occupies an active area of 0.017 mm2 and is able to supply a maximum current of 100 mA from a 1.2 V supply. Despite having low quiescent current performance, the transient response is not compromised significantly. The measured output change is 68.8 mV when the load current is switched from 0 to 100 mA in 300 ns with a capacitive load of 100 pF. It is able to recover from transient response within 6 μs. Finally, the introduction of a low-impedance loading network circuit is dedicated to enhance the stability or to improve light-load efficiency. To demonstrate the proposed circuit technique, it is applied to the design of an OCL-LDO regulator. The simulation results have confirmed the circuit operation in 0.18 μm CMOS technology. The simulated quiescent current is 14 μA at a 1.2 V supply, no minimum loading current is required. Therefore, the current efficiency at light load is enhanced. The proposed design technique can be applied to LDO regulator with any structure. All the proposed works in this thesis consume very small quiescent currents whilst having a good balanced performance metrics when compared with the representative prior-art works. It has validated that they are useful for on-chip applications. DOCTOR OF PHILOSOPHY (EEE)

In recent years, there is a great deal of interest in the three-dimensional integrated circuit (3D IC). By stacking multiple active device layers with vertical interconnect, 3D IC technology provides great opportunities for designers to meet power and performance requirements. In this research, the innovative 3D IC technology is employed as a basic tool. In addition to the conventional horizontal dimension, active devices are stacked in the vertical dimension in 3D IC technology. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, so that delay, power consumption, and area can be reduced. The design problem of miniaturized wireless sensor node has been explored and a digital core design in wireless sensor node is proposed in this work. The design aims to provide an efficient solution for recording users’ bio-vital data, as well as to transmit, extract and deposit the information on the platform. This capability serves to monitor the progression of chronic diseases. The 3D architecture for a wireless sensor node will be discussed in-depth and the impact of 3D-integration technology on conventional digital circuit design will be demonstrated in this project too. Through silicon via (TSV) based 3D integration technology is employed as the vertical interconnect methodology. The proposed design methodologies described in this thesis are intended to strengthen the 3D design capabilities, making this fascinating technology a promising solution for future integrated systems. Functional tests were conducted to validate the overall systems usability and modularity and the measured results proved that reliable data transfer and continuous bio-vital data monitoring can be consistently achieved. The measured results validated the approaches chosen, and verified that the system is useful in patient monitoring application. The next phase of the work will be to implement the proposed digital core design in 3D wireless sensor node in field programmable gate array (FPGA). MASTER OF ENGINEERING (EEE)

Nowadays, highly integrated electronic products are becoming part and parcel of our daily life. With the technology improvement in Integrated Circuit (IC), more complicated functions can be incorporated into very large-scale systems, rendering the electronic products more powerful and entertaining. The increasing IC size and function blocks bring in new design challenges for its power management circuits, such as accuracy, efficiency, response speed, input and output voltage ranges, and driving capability. The State-of-the-art DC-DC regulators usually combine several control methods in order to fulfill all of the above-mentioned specifications. For instance, a dual mode DC-DC converter applies the Pulse-Width-Modulation (PWM) control method at heavy load condition and shifts to Pulse-Frequency-Modulation(PFM) control at light load condition. This hybrid dual mode operation can indeed improve the efficiency over a wide loading range. However, dual mode operation also implies more complicated circuits design and increased fabrication cost. Apart from it, uncontrolled switching frequency under PFM condition will cause unwanted Electron-Magnetic interference(EMI) issues and challenges of input filter design. Under PWM condition, a power-hungry error amplifier is generally required which will limit the transient response speed. Considering the existing drawbacks of conventional control methodologies and the future development of modern Power Management Units(PMU), several control methods were proposed in this thesis to improve the performances of switching-inductor based DC-DC converters targeting for different specifications. In the beginning, a PWM DC-DC converter works in Discontinues-Conduction-Mode a(DCM) at light load condition was conducted in my research. With a novel Zero-VoltageDetector (ZVD) implemented in this regulator, fast sensing and quick comparison were realized in order to avoid inverse conduction of inductor current. The time delay of ZVD sensing and comparing activities were only about 6ns, and a power conversion efficiency >85% was achieved over a loading range from 10mA to 250mA. Subsequently, in order to be compatible with the development of modern DC-DC regulators, the conventional control methods based on linear control mechanism may not be the best options when dealing with frequently switched loadings. Take this limitation into concern, two designs of high-speed converters with hysteretic non-linear control mechanisms were proposed and conducted. Particularly, switching frequency locking properties were introduced into these two converters with a frequency locking range about several MHz. This hysteretic control method with frequency locking ability is called fixed switching frequency hysteretic control. The proposed designs were fabricated using 0.18mm CMOS process, and their switching frequencies were maintained at 10MHz with less than ±1% variations. The transient recovery time of Design I is about 2ms, and it is only about 0.3ms for Design II. A peak power efficiency of 91% was achieved over a loading range from 100mA to 600mA. Compared to conventional hysteretic PFM controls, the proposed designs have a fixed switching frequency, so the electromagnetic interference (EMI) problems can be greatly reduced and the challenges on input filter design can be minimized. Furthermore, the proposed fixed frequency hysteretic non-linear control topologies can be further used for multi-phase interleaved DC-DC converters applications to provide large current drive capabilities. bIn this thesis, the background information about DC-DC regulators was introduced, and then the motivations and objectives to conduct this research were inspired. Retrieving and analyzing existing technologies, the above mentioned three designs were fully discussed from conceptual ideas, followed by circuits implementations, and all the way to system simulations and measurements. Both advantages and disadvantages will be presented for further study. Doctor of Philosophy

Deep neural networks have achieved phenomenal successes in vision recognition tasks, which motivate the deployment of deep learning in portable and smart wearable devices. To overcome the fundamental challenges of power and resource limitation, application-specific integrated circuit accelerators have emerged to compact the model and use lower precision arithmetic to increase the throughput of computation with reduced power consumption. Although very high energy efficiency has been achieved by removing redundant weights, compressing data and even sacrificing timing margin, such trend in hardware acceleration that pushes the deep learning systems to the error threshold can be disastrous for the tasks they performed due to failure or degraded performance of circuit components. Concerned by the lack of attention on the evolving unreliability effects in artificial intelligent accelerators implemented by the continuously scaled CMOS technology, this paper is the first to evaluate the effect of circuit aging on performance degradation of deep learning accelerator. Our findings indicate that DNN system running at their peak throughput rate can experience up to 84% accuracy drop after a year of aging and the accumulation of errors aggravates with the depth of learning. It is also found that relaxation of throughput rate can slow down the loss of classification accuracy considerably. MOE (Min. of Education, S’pore) Accepted version

In this paper, a novel in-pixel event-driven physical unclonable function (PUF) is presented for the rapidly developed CMOS dynamic vision sensor (DVS). Different from traditional widely reported PUF implementations with additional dedicated silicon area, power consumption and peripheral circuitries, the proposed implementation extracts PUF based on the original gain amplifier existing in the mainstream DVS pixel, which is necessary to amplify the front-end logarithmic photoreceptor’s relatively weak output signal, according to the ratio of the in- pixel capacitor pair. With any ON/OFF event generated and the corresponding DVS pixel fired asynchronously, the DVS pixel’s own gain amplifier will be reset in order to capture the next possible event. Due to the inevitable variation of the semiconductor fabrication process, the reset voltages of different DVS pixels’ gain amplifiers are slightly different. A bidirectional counter based analog-to-digital converter is customized to digitize the successively fired pixel pair with the sign bit representing the PUF bit (i.e. the reset voltages’ difference). Moreover, the proposed implementation is validated using a standard 0.18μm CMOS process in Cadence. According to the extensive post-layout simulation results, the uniqueness is calculated to be 49.97%. With the operating temperature varying from −40◦C to 120◦C and supply voltage varying from 1.7V to 2.1V, the worst-case reliability is reported to be 96.48% and 97.27%, respectively. Meanwhile, its superior randomness is also verified using the NIST test suite. MOE (Min. of Education, S’pore) Accepted version

Energy-efficient has been an interested research for decades. For fundamentals circuits, resistors in a circuit always dissipate energy when they have current flow and it decreases energy efficiency. When the resistive circuits are in transient state, energy dissipation is usually inevitable. However, it can be minimized. Either energy dissipation or input energy are dependent with voltage and current functions in the circuits. Therefore, there are the most energy-efficient functions, the functions that minimize the input energy (or the energy dissipation). The functions can be obtained by applying calculus of variations, a powerful mathematics theory for functional optimization. Once the most energy-efficient functions are obtained, the lowest input energy can be calculated. For a series RC circuit, one of the simplest first order circuit, the most energy- efficient input current function and input voltage function are derived and proved to be a constant function and a raised ramp function respectively. The optimization by using calculus of variations is expanded to any first order passive circuits. It turns out that the most energy-efficient function for general first order circuits is hyperbolic family. The lowest input energy is calculated and stated as corollaries. The corollaries are essentials to provide insight into transient duration analysis. The transient duration analysis is performed for three cases of increasing, decreasing and unchanging total stored energy. All these cases are analyzed comprehensively. In each case, it is further divided into two sub cases of (un)changing without and with zero crossing. The analysis reveals two important circuit behaviors which are speed and energy trade-off and energy flow. It is shown that the speed and energy trade-off may be violated under certain conditions. The energy flow of the circuit is discussed thoroughly and a zero-energy transient duration that is defined as a transient duration with total input energy being zero is derived. All the analysis can be summarized into a single digram called the transient duration diagram. The digram reveals important relationships between the circuit parameters in the transient duration analysis. Not only first order circuit that are optimized, but also second order circuit. Series LC circuit and parallel LC circuit are chosen to be optimized because they are typical second order circuits. The most energy-efficient functions of the circuits can be catego- rized into three modes which are (i) hyperbolic mode, (ii) hyperbolic and linear mode and (iii) hyperbolic and trigonometric mode. Each mode are discussed and theirs tran- sient responses are illustrated. The lowest input energy are evaluated and the transient duration analysis are done rigorously. Finally, generalization of the most energy-efficient functions and the lowest input energy for any order circuits is drawn. A dummy function is introduced which is essential for generalization. The most energy-efficient input functions in terms of the dummy function are proposed as well as the lowest input energy. General formulas or general procedure for determining the most energy-efficient functions and the lowest input energy for any orders circuits is explained. Using of the general formulas is discussed. Applying the general formulas of RC chain circuit is explained thoroughly. Doctor of Philosophy

Finite-state machine (FSM) is widely used as control unit in most digital designs. Many intellectual property protection and obfuscation techniques leverage on the exponential number of possible states and state transitions of large FSM to secure a physical design with the reason that it is challenging to retrieve the FSM design from its downstream design or physical implementation without knowledge of the design. In this paper, we postulate that this assumption may not be sustainable with big data analytics. We demonstrate by applying a data mining technique to analyze sufficiently large amount of data collected from a full scan design to identify its FSM state registers. An impact metric is introduced to discriminate FSM state registers from other registers. A decision tree algorithm is constructed from the scan data for the regression analysis of the dependency of other registers on a chosen register to deduce its impact. The registers with the greater impact are more likely to be the FSM state registers. The proposed scheme is applied on several complex designs from OpenCores. The experiment results show the feasibility of our scheme in correctly identifying most FSM state registers with a high hit rate for a large majority of the designs. Ministry of Education (MOE) Accepted version This work was supported in part by the National Natural Science Foundation of China under Grant 61672182, the Guangdong Natural Science Foundation under Grant 2016A030313662, and in part by the Singapore Ministry of Education Tier 1 Grant MOE2018-T1-001-131 (RG87/18).