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In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB. [ABSTRACT FROM AUTHOR]

A low-power and compact carbon nanotube field-effect transistor (CNTFET)-based K -band electronically tunable band-pass filter (BPF) is presented. The filter is designed using second-generation multiple-output current-controlled current conveyor (MOCCCII). The presented active only current-mode BPF employs three MOCCCIIs and two CNTFETs as capacitors. This BPF can be tuned by varying the parasitic resistance of MOCCCIIs via the control current. The designed current-mode tunable BPF is simulated in an advanced design system (ADS) using the Stanford CNTFET model with the extension of noise and manufacturing process variation. The filter achieves a 21–23 GHz tuning frequency range, with a minimum noise figure of about 11.09 dB. The 1-dB compression point and input-referenced third-order intercept point are −19.28 and −8.4 dBm, respectively. This compact filter consumes only 145.7 μ W power at ± 0.5 V supply voltage at room temperature. The temperature analysis shows good thermal stability. The Monte Carlo analysis demonstrates the good process variation stability of the filter. The suggested BPF can be thought of as the first fully active BPF that is a candidate for K -band communication applications with future advances in the fabrication process for CNTFET. [ABSTRACT FROM AUTHOR]

Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18 μ m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9 dB can be achieved for a bandwidth of 50 GHz in 0.18 μ m RF-CMOS technology. In this amplifier, parameters S 1 1 , S 2 2 and S 1 2 are − 12, − 10 and − 18 dB, respectively; noise figure is 4.3–5.8 dB, and P 1 d B is +4 dBm. This amplifier consumes 220 mW power and has a chip area of 0.58 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a new extended high-efficiency-range Doherty power amplifier (DPA) with a main and only a single auxiliary amplifier. In order to extend the output high-efficiency range with a high-efficiency level, asymmetrical cells are employed as the main and auxiliary amplifiers in class-F and class-C complex combining load (CCL) methodology, respectively. To verify the proposed methodology, a DPA with 12-dB output back-off (OBO) is designed and fabricated for wideband code division multiple access (WCDMA) applications. Large-signal continuous-wave measurement results show the power gain of about 11 dB with a drain efficiency of 59.9% at 12 dB of OBO. A two-tone test exhibits a third-order intermodulation distortion (IMD) of lower than − 2 1 dBc. Modulated wave measurements show over 55% of average drain efficiency and an adjacent channel leakage power ratio (ACLR) of lower than − 2 7. 5 dBc at an output power level of 31.5 dBm. [ABSTRACT FROM AUTHOR]

This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40GHz bandwidth (BW) in 0.18-m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S of 6.4dB, 3-dB BW from DC up to 40GHz. It also has a minimum noise figure (NF) of 4.27dB, one dB compression point (P of 3.5dBm, a high reverse isolation S of less than 15dB, an input return loss S and output return loss S of less than 16 and 12dB, respectively. It consumes 115mW and occupies a total active area of 0.27mm2. [ABSTRACT FROM AUTHOR]

This paper presents a new tail current-shaping technique to improve the phase noise of an LC quadrature VCO (LC-QVCO) based on Gaussian pulse generator (GPG). The GPG makes a narrow pulse from oscillator sinusoidal output and injects it back to gates of tail transistors to reduce the root-mean-square (RMS) value of impulse sensitivity function (ISF) and to improve phase noise. It will be shown that by utilizing a GPG, total phase noise improvement will be as high as 6dB. The proposed circuit was designed and simulated by ADS simulator using 0.18m TSMC RF CMOS design kit. The phase noise's at 3MHz frequency offset and carrier frequencies of 2.43GHz and 2.6GHz are -141dBc/Hz and -135dBc/Hz, respectively, while the total power consumption is 14mW under 1.8V supply voltage. Tuning range is from 2.43GHz to 2.6GHz. The figure of merit (FOM) values for the proposed LC-QVCO at 3MHz frequency offset are -187.6dBc/Hz and -182.3dBc/Hz for 2.43GHz and 2.6GHz carrier frequencies, respectively. [ABSTRACT FROM AUTHOR]

We propose a feedback type oscillator and two negative resistance oscillators. These microwave oscillators have been designed in the S band frequency. A relatively symmetric resonator is used in the feedback type oscillator. The first negative resistance oscillator uses a simple lumped element resonator which is substituted by a microstrip resonator in the second oscillator to improve results. The negative resistance oscillator produces 4.207 dBm and 7.124 dBm output power with the lumped element resonator and microstrip resonator respectively, and the feedback type oscillator produces −10.707 dBm output power. The feedback type oscillator operates at 3 GHz with phase noise levels at −83.30 dBc/Hz and −103.3 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively. The phase noise levels of the negative resistance oscillator with the lumped element resonator are −94.64 dBc/Hz and −116 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively, at an oscillation frequency of 3.053 GHz. With the microstrip resonator the phase noise levels are −99.49 dBc/Hz and −119.641 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively, at an oscillation frequency of 3.072 GHz. The results showed that both the output power and the phase noise of the negative resistance oscillators were better than those of the feedback type oscillator. [ABSTRACT FROM AUTHOR]