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In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

Emerging applications in D-band (110–170GHz) demand amplifiers with high gain-bandwidth (GBW) products. In this frequency range, the cascode stage offers superior available gain, thanks to the high output impedance, but the design of the output matching network entails a GBW tradeoff. The issue is deeply investigated in this work. Simple, closed-form equations for gain and bandwidth as a function of the load reflection coefficient are derived, leading to the following design insights: 1) for maximum gain and bandwidth, the output matching network should be implemented with positive (magnetic) reactances; 2) with lossy reactances, an optimal load reflection coefficient exists to maximize the power gain, ${\Gamma '_{L-{\mathrm{ opt}}}}$ ; and 3) by selecting ${\Gamma '_{L} , the bandwidth increases quickly with a marginal gain penalty, finally enhancing the GBW product. Leveraging the results of the analysis, single-stage and multistage stagger-tuned amplifiers are implemented in SiGe BiCMOS technology. Two- and three-stage amplifiers demonstrate more than 60GHz bandwidth with 20 and 28dB gain, respectively, corresponding to 700GHz and 1.7 THz GBW. Normalizing gain and bandwidth to the number of stages and technology $f_{\max }$ , the resulting figure of merit is remarkably higher than previously reported silicon amplifiers in the same band.

In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high ION( $1.231\times 10^{-4}\text{A}/\mu \text{m}$ ) and ION/IOFF ratio ( $2.52\times 10^{5}$ ) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having $\text{I}_{\mathrm {ON {}}}(1\times 10^{-7}\text{A}/\mu \text{m}$ ) and ION/IOFF ratio ( $1\times 10^{2}$ ). It has been observed that there is more than 100 times improvement in cutoff frequency ( $f_{\mathrm {T}}$ ), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency ( $f_{\mathrm {max}}$ ) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98% and 33.33% in switching ON and OFF delays respectively in the proposed device-based inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues.

A high-performance CMOS, fully balanced second-generation current conveyor (FBCCII) is proposed to exclusively use CCII circuits in integrated circuit applications. In the proposed circuit, a current folding technique is applied to a fully balanced version of transconductance amplifier. The proposed FBCCII consumes 84 $$\upmu $$ W of power and has an open-loop gain of 47.83 dB with 62.9 $$^\circ $$ of phase margin. The simulated input referred noise is 155 nV/ $$\sqrt{\text {Hz}}$$ @ 1 KHz and has a unity gain bandwidth of 39.8 MHz. A common mode feedback (CMFB) circuit is also proposed to improve the dynamic range of the proposed FBCCII circuit by 50 $$\%$$ as compared to the circuit with-out CMFB. The CMFB consumes 170 $$\upmu $$ W of power and has a bandwidth of 60 MHz. The proposed circuit is simulated using standard 180 nm CMOS process operating at $$\pm \,0.5$$ V supply voltage. To verify the effectiveness of the approach, a fully differential variable gain amplifier with tunable gain from 0 to 30 dB is designed. Also, a bandpass filter with quality factor = 4 and bandwidth of 10 MHz is designed using the proposed FBCCII. A novel low-pass filter (LPF) using the proposed FBCCII is designed for bio-medical applications. The proposed LPF is a second-order filter with the cut-off frequency of 55 Hz and 121 nV/ $$\sqrt{\text {Hz}}$$ of input-referred noise. The LPF is designed at a supply voltage of $$\pm \, 0.5$$ V, and the spurious free dynamic range of proposed LPF is 85 dB. The figure of merit of the LPF is 7.3 fJ. The layout area of the proposed FBCCII design is 6889 $$\upmu $$ m $${^2}$$ ( $$83\,\upmu \text {m} \times 83\,\upmu \text {m}$$ ).

This paper presents a wideband and highly linear transimpedance amplifier (TIA) with a high-speed, current-efficient transconductance amplifier and multi-order filtering. The proposed TIA employs a Rauch biquad structure and incorporates an operational transconductance amplifier with an improved feedforward frequency compensation in a nested configuration. The Rauch biquad TIA architecture improves the out-of-band (OOB) selectivity, achieving a high OOB IIP3 of the TIA. The proposed feedforward compensation scheme is effective only at high frequencies and thus further enhances the gain bandwidth product of the transconductance amplifier. The current re-use technique improves the power efficiency of the feedforward stage. The prototype circuit was designed in the TSMC 65nm CMOS technology. The TIA achieves a bandwidth of 80 MHz and an OOB IIP3 of 26.8 dBm with a power consumption of 14.2 mW from a supply of 1.8 V while occupying a core area of 0.037 mm2.

Design and simulation of an improved recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The new idea is based on minor changes in the conventional structure. Our improved amplifier is capable to enhance DC gain and unity gain bandwidth (UGBW) in the same −3dB frequency as for RFC structure. Moreover, fast-settling time, input-referred noise, total harmonic distortion (THD) and performances of power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are also improved. Simulation results in 90 nm CMOS process indicate that the proposed amplifier has about 2 times the unity gain bandwidth (360 versus 175 MHz) and also has twice gain boosting (68.6 versus 62.5 dB) in the same −3 dB frequency and capacitor load of 10 pF @1.2 V power supply. The results also demonstrate a good figure of merit (FOM), and low sensitivity of temperature and power supply variations for the proposed amplifier.

This study introduces the design of a practical three-stage operational amplifier (op-amp) using nested Miller compensation, particularly for piezoelectric actuators. Driving a piezoelectric actuator represents a challenge in amplifier design due to its large capacitive nature. A stable piezo driver needs to be free of oscillations and phase lag. Direct feedback compensation using a conventional Miller capacitor is an effective method as long as the capacitance of the load is considerably close to the value of the Miller capacitor. However, using a large capacitor causes a decrease in the slew rate and gain bandwidth. To avoid this, our design focused on the utilization of nested Miller compensation technique. A prototype of the design working at 100V peak to peak voltage (Vpp) is implemented using commercial off-the-shelf (COTS) components. The measurements show the successful driving capability and step-response of the op-amp design. In the design, Widlar current source is also utilized for thermal stability and short circuit protection. According to simulation results, the proposed op-amp has a slew rate of 0.5 V/μs, an open loop gain of 90dB with 3MHz Gain Bandwidth Product (GBP) and phase margin of 77°, and a common mode rejection ratio (CMRR) of 62dB.

In this article, we propose an extended-source double-gate tunnel field-effect transistor (ESDG-TFET) to enhance the dc and analog/RF performance. The source of an ESDG-TFET is extended into channel to increase the line and point tunneling in the device at the source–channel junction. 2-D simulations in the TCAD tool (ATLAS) are carried out to analyze and investigate the performance of the proposed device. At optimized device structural parameters, the ESDG-TFET provides a low threshold voltage of 0.42 V, a low subthreshold swing of 12.24 mV/decade, and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of $2.57\times 10^{{12}}$ . Furthermore, the proposed device achieves a maximum transconductance of 238 $\mu \text{S}/\mu \text{m}$ , a cutoff frequency of 37.7 GHz, and a gain bandwidth product of 3.4 GHz.

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance ( g m ) cut-off frequency ( f T ) , gain bandwidth product and maximum oscillating frequency ( f max ) . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 $\mu$A. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it may be noted that the proposed amplifier achieves a gain of 76.24 dB and unity gain bandwidth of 74.7 MHz with an input referred noise and slew rate of 139.2 $\mu V_{rms}$ and 64.05 V/$\mu$s respectively. The proposed amplifier occupies an area of 2760 $\mu m^{2}$.

This paper presents a technique to enhance an overall performance of advanced recycling folded cascode operational transconductance amplifier (RFC OTA). It adopts an input stage comprising a cross coupled MOS differential pair biased by a constant DC current source in addition to an adjustable floating voltage source. The proposed modification shows a substantial improvement in transconductance leading to boost dc gain, gain-bandwidth and slew rate of conventional FC-OTA. The structure is designed and implemented in 0.18 μm CMOS technology. In addition to transconductance enhancement, a remarkable improvement in a phase margin is achieved using a Miller compensation technique to ensure the stability of OTA. The simulation results demonstrate the performance of the proposed OTA with 72 dB gain and unity gain bandwidth of 128 MHz for a capacitive load of 10 pF. The modified RFC OTA shows 550% improvement in gain bandwidth product (GBW) and 20 dB hike in the gain compared to the conventional FC-OTA, which has 19.85 MHz GBW and 51.9 dB respectively. The Miller compensated OTA shows 36% improvement in a phase margin compared to non-compensated OTA with a slight reduction of 6% in GBW.

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency ( f T ), gain bandwidth product, transconductance generation factor and so on. The higher I ON / I OFF ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher g m / I D ratio ensures lower bias power of an amplifier.

This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator.

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

In this work, we demonstrate In0.52Al0.48As top/backside-illuminated avalanche photodiodes (APD) with dual multiplication layers for high-speed and wide dynamic range performances. Our fabricated top-illuminated APDs, with a partially depleted p-type In0.53Ga0.47As absorber layer and thin In0.52Al0.48As dual multiplication (M-) layer (60 and 88 nm), exhibit a wide optical-to-electrical bandwidth (16 GHz) with high responsivity (2.5 A/W) under strong light illumination (around 1 mW). The measured bias dependent 3-dB O-E bandwidth was pinned at 16 GHz without any serious degradation near the saturation current output. To further increase the speed, we downscaled the active diameter and adopted a back-side illuminated structure with flip-chip bonding for batter optical alignment tolerance. A significant improvement in maximum bandwidth was demonstrated (25 versus 18 GHz). On the other hand, we adopted a thick dual M-layer (200 and 300 nm) and 2 μm absorber layer in the APD design to circumvent the problem of serious bandwidth degradation under high gain (&gt, 100) and high-power operation which significantly enhanced the dynamic range. Due to dual M-layer, the carriers could be energized in the first M-layer then propagate to the second M-layer to trigger the avalanche process. In both cases, despite variation in thickness of the absorber and M-layer, the cascade avalanche process leads to values close to the ultra-high gain bandwidth product (GBP) of around 460 GHz with a responsivity of 0.4 and 1 A/W at unit gain for the thin and thick M-layer devices, respectively. We successfully achieved a good sensitivity of around −20.6 dBm optical modulation amplitude (OMA) at a data rate of 25.78 Gb/s, by packaging the fabricated APDs (thin dual M-layer (60 and 88 nm) version) with a 25 Gb/s trans-impedance amplifier in a 100 Gb/s ROSA package. The results show that, the incorporation of a dual multiplication (M) layer structure in the APD opens a new window to obtaining the higher GBP in order to meet the requirements for high-speed transmission without the need of further downscaling the multiplication layer.

In this paper we unveil of a new structure in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is paralleled with a Tunneling Field Effect Transistor (TFET) to increase on-state current. In order to enhance tunneling current injection rate in the device, workfunction engineering in gate and substrate electrodes and doping engineering in channel (source pocket) are utilized. For further on-state current enhancement of device, thermionic injection mechanism is used by incorporating a MOSFET in the structure. In addition, hetero gate dielectric is used to reduce parasitic capacitances. Our analysis show PTM-FET transistor has several excellences in comparison to DW HGD SP TFET in terms of transconductance, Ion/Ioff current ratio, short channel effects like DIBL, Early voltage, maximum transducer power gain, unilateral power gain, gain bandwidth product, unity gain frequency and parasitic capacitances. The mentioned advantages for PTM-FET transistor can be a window of utilizing this device in both low power and high performance integrated circuit applications.

This paper presents the description and analysis of the design and HSPICEbased simulation results of very low-voltages (LVs) power supplies and highperformance specifications CMOS gate-driven (GD) operational amplifier (OpAmp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from -0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 ⁄√ at 1MHz, the positive slew rate is 11.37 ⁄ , the negative slew rate is 11.39 ⁄ , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

This paper proposes a novel operational amplifier (OPA) voltage-controlled oscillator (VCO) circuits on the basis of impedance converters. The VCO can operate over a frequency range exceeding unity-gain bandwidth due to the location of the tank circuit, not at the output of the OPA, but at the noninverting input. The paper presents the mathematical modeling of oscillated amplitude and start-up conditions. The simulation results confirm the theoretical achievements. The designed and simulated VCO uses an ultra-low noise wideband OPA LMH6629MF, covers a frequency band between 0.830 GHz and 1.429 GHz, and exhibits a maximum in-band total harmonic distortion (THD) of 1.7%. It has a maximum in-band phase noise of &minus, 139.3 dBc/Hz at 100 kHz offset frequency and has an outstanding value of a standard figure of merit (FoM) of &minus, 198.6 dBc/Hz. The zero-peak amplitude of output voltage is from 3.2 V to 4 V for all generated frequencies at a supply voltage of &plusmn, 5 V. The fabricated prototype-oscillator based on OPA LMH6624 operates at a frequency of 583.1 MHz with a power level of 0 dBm.

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/&mu, m to 0.1 fF/&mu, m. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

In this paper, a folded cascode operational amplifier is designed and analysed by using 0.13 µm CMOS technology. Several analyses such as DC analysis and AC analysis are carried out to analyse the performances of the proposed folded cascode op-amp. Through the simulation of Mentor Graphics, under 3.3 V power supply, the circuit’ s DC gain is 32.3590 dB, the phase margin is 83.754 degree with high stability, the bandwidth is larger than 10 MHz, the unity gain bandwidth is as high as 906.8953 MHz and the power dissipation is 86.9774 mW.

A super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date. This work has been supported in part by grant TEC2016-80396-C2 (AEI/FEDER).

Nowadays, low power operational amplifiers (op-amp) are highly demand for most of the applications such as in medical and communication system. In this project, two stage op-amp is designed and operated at 1.8 V supply voltage. The supply voltage is scaled down to reduce the power dissipation of the op-amp. This is because the power will be high when there is a large supply voltage. The design is simulated and analysed using Mentor Graphic Pyxis software. This two stage op-amp is designed using the Silterra 0.13 µm process technology. The operational amplifier provides a Direct Current (DC) gain of 21.18 dB and a unity gain bandwidth of 6.31 MHz. The gain margin obtained from the op-amp is 14.07 dB and the phase margin of the op-amp is 94.26 ° for 3 pF compensation capacitor and 10 pF load capacitor. The result shows that circuit able to work at 1.8 V power supply voltage and the total power dissipation for the op-amp is 5.35 mW.

This brief presents the principle and the first experimental results of the multiple-input bulk-driven (MIBD) MOS transistor (MOST) suitable for extremely low-voltage low-power integrated circuits. The MIBD MOST offers significant reduction in circuit complexity, power consumption and extension of the input common-mode range (ICMR). To confirm the benefits of the MIBD MOST, a differential difference amplifier (DDA) with very simple CMOS topology has been designed and fabricated in a standard n-well 0.18 µm CMOS process from TSMC with total chip area 226 µm × 78 µm. The DDA is supplied with 0.5 V and consumed only 1.23 µW, while the ICMR is rail-to-rail. The measured open-loop dc gain is 62 dB, the gain bandwidth product is 56.4 kHz, and the total harmonic distortion is 0.2% @ 1 kHz for 400 mV peak-to-peak input sine wave.

Proposed in this paper is design and analysis of an enhanced recycling folded cascode (RFC) Op-Amp. This structure is achieved using connecting two nodes and eliminating some devices in the conventional RFC. This effect enhances the DC gain with increasing output resistance of differential pair compared to the conventional RFC circuit. In the same − 3 dB frequency, the unity gain bandwidth is also increased. Moreover, for the same slew rate and input referred noise performance, other proposed improvements are the fast-settling time and total harmonic distortion. Hspice simulation results in 90 nm CMOS standard technology demonstrate that the proposed amplifier has 1.2 times the unity gain bandwidth (190 vs. 160 MHz) and also has twice gain boosting (66.2 vs. 59.5 dB) in the same − 3 dB frequency, power supply (1.2 V) and driving capacitor load of 5 pF.

Using MOSCAPs for compensation can reduce the area needed for their implementation. However; these capacitors are highly nonlinear and their value changes when the voltage across their terminals is changed. Different compensation topologies do not exhibit equal sensitivity to the time-dependent variation of MOSCAP compensation capacitors. Therefore; the selection of a proper compensation technique is considered as an important step before its implementation. In this paper, the goal is to study the existing compensation techniques and their behavior in the presence of compensation capacitor uncertainty and MOSCAP nonlinearity. For such regard, opamps are first designed for equal performance metrics such as: gain bandwidth product, phase margin and settling time. Then the sensitivities of the different structures are evaluated. Ultimately, the least sensitive structures can be chosen as the best choice for implementation. Based on the knowledge of the authors, no such thorough analysis has been ever performed before. A state-space model is suggested to analyze different compensation topologies and to calculate the harmonic distortions and find the most robust structures. These results are compared with circuit level results. It is shown that the CFCC compensation method can lead to creation of least harmonic distortion.

An output-capacitorless low-dropout regulator (OCL-LDO) using enhanced multipath nested Miller compensation with embedded feedforward path for system-on-chip (SoC) applications is presented in this paper. While state-of-the-art LDOs are restricted to low-frequency operation with a maximum unity-gain bandwidth (UGB) typically ranging from several hundred kilohertz to no higher than 10 MHz even in advanced technologies (65 nm or beyond), the prototype fabricated in a standard 130-nm CMOS process features over 100-MHz UGB for all loading conditions up to 25-mA output current while consuming a quiescent current of 112 μ A. With this ultra-wide bandwidth, the proposed LDO achieves 200-ps response time for load transient with 300-ps edge time. The extension of UGB also magnificently contributes to improvement of power-supply rejection (PSR), making it comparable to OCL-LDOs that use ripple-feedforward techniques to specifically boost PSR or LDOs with large off-chip decoupling capacitors, while enjoying much faster speed. The chip area is 0.008 mm2.

This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a dc gain above 47 dB and a figure-of-merit better than 960 MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130-nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6 MHz*pF/mA.

Objectives: This paper presents the design and analysis of differential input stage to design low voltage operational amplifier, where bulk-driven MOSFETs are incorporated in the current mirror. Methods/Analysis: To be possible to operate circuit at lower supply voltage, body-driven transistors are used to design current mirror. Circuit is designed using 180nm (Complementary Metal Oxide Semiconductor) CMOS n-well technology and BSIM 3v3 Specter models are used to analyze the design. Performance parameters are validated by simulations. Findings: The amplifier shows DC openloop gain of 44 dB. The Unity Gain Bandwidth (UGB) is 3.3 MHz with a phase margin of 87.8°. The amplifier exhibits Common-Mode Rejection Ratio (CMRR) of 62 dB. The input referred spot noise voltage at 1KHz is 42.46nV/√Hz. These results are obtained with a supply voltage of 1V. Average power consumption of the amplifier is 36.36 μW under 10 pF load condition, which makes it suitable for low voltage and low power applications. Improvement: Gain can be further improved by employing cascode current mirror in the presented amplifier as it will increase output impedance. Keywords: Analog and Mixed-signal system, Bulk-driven Current Mirror, Differential Input Stage, Low-voltage Operational Amplifier, CMOS

This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal-oxide-semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-of-the-art designs.

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz. En este trabajo se presenta el diseño y caracterización de un nuevo seguidor de voltaje analógico para aplicaciones de bajo voltaje. La idea principal aquí desarrollada, está basada en el Seguidor de Voltaje “Volteado” y el uso de técnicas de compuerta casiflotante para lograr un funcionamiento de clase AB. Usando una tecnología CMOS de 0.5 μm, se simuló y se fabricó una celda de prueba. Cuando el circuito propuesto se alimenta con VDD = 1,5 V, este presenta un consumo de potencia de tan solo 413 μW. Las mediciones y los resultados experimentales muestran un producto ganancia-ancho de banda de 10 MHz y una distorsión harmónica total de 1,12 % a 1 MHz.

A symbolic analysis is presented to study a gain-boosted telescopic operational transconductance amplifier (OTA) with cross-coupled capacitor (positive feedback) across an auxiliary op-amp. The effects of positive feedback capacitor (PFC) on the pole-zero doublet introduced by the auxiliary op-amp are explored using analytical techniques and simulations. A complete transfer function of the OTA with PFC across the auxiliary op-amp is derived and verified through circuit simulations. The results obtained from circuit simulation and modelled transfer function show good agreement with each other. Furthermore, the analytical expressions for the feedback capacitor in terms of pole-zero locations, unity gain bandwidth (UGBW) and phase margin (PM) are presented. It is shown that UGBW, PM and settling behaviour of the OTA can be tuned by the PFC. A systematic design approach to improve the PM and settling behaviour is discussed. On the basis of the theory presented, 17% improvement in 0.01% settling time is demonstrated.

In recent years, phototransistors have considerably expanded their field of application, including for instance heterodyne detection and optical interconnects. Unlike in low-light imaging, some of these applications require fast photodetectors that can operate in relatively high light levels. Since the gain and bandwidth of phototransistors are not constant across different optical powers, the devices that have been optimized for operation in low light level cannot effectively be employed in different technological applications. We present an extensive study of the gain and bandwidth of short-wavelength infrared phototransistors as a function of optical power level for three device architectures that we designed and fabricated. The gain of the photodetectors is found to increase with increasing carrier injection. Based on a Shockley-Read-Hall recombination model, we show that this is due to the saturation of recombination centers in the phototransistor base layer. Eventually, at a higher light level, the gain drops, due to the Kirk effect. As a result of these opposing mechanisms, the gain-bandwidth product is peaked at a given power level, which depends on the device design and material parameters, such as doping and defect density. Guided by this physical understanding, we design and demonstrate a phototransistor which is capable of reaching a high gain-bandwidth product for high-speed applications. The proposed design criteria can be employed in conjunction with the engineering of the device size to achieve a wide tunability of the gain and bandwidth, hence paving the way toward fast photodetectors for applications with different light levels.

In this paper dynamic biasing technique is used for the enhancing the slew rate of the designed Op-Amp. The proposed FinFET based Op-Amp has been verified through Hspice simulator in the standard 45nm Silicon on Insulator FinFET library. The proposed op amp has two stages Miller compensated configuration. A biasing circuit (DSB circuit) is used for dynamic switching of the biasing voltage of the op amp. This leads to lower power consumption, wide ICMR range, and high gain stability. The proposed op amp has a power consumption of 661.83 μW. It has a dual supply voltage of -1.0V and 1.0V. The input common mode range (ICMR) is -800 mV to +900 mV. The Op-Amp has a slew rate of 1.5 KV/μs. Voltage gain of the op amp is 90.4dB. Due to the use of SOI FINFET devices the op amp has relatively less leakage current as compared to similar bulk MOSFET device op amps. The op amp has unity gain bandwidth of 1.27 GHz. Thus, it can be used to transmission and processing of audio and video signals.