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Current mirrors (CMs) are essential building blocks for biasing electronic circuits. The present work demonstrates that errors in mirroring ratios increase at cryogenic temperatures, for all types of SiGe HBT and CMOS CMs. The sources of errors are attributed to the mismatch in operating conditions and a combination of process variations and layout effects. In particular, the effects of layout on device current are found to increase significantly at low temperatures, which can potentially contribute more to the CM error than process variations. Among all investigated CM configurations, the simple CM based on large geometry SiGe HBTs is the most versatile option with small errors, a large operational range, and a simple layout.

This investigation examines the physical mechanisms that can increase the variability of both p-n junctions and silicon–germanium heterojunction bipolar transistors (SiGe HBTs) at cryogenic temperatures. The important operative mechanisms responsible for device parameter variability include bandgap narrowing due to heavy doping, mechanical stress, and the Ge profile. The impact of direct tunneling on cryogenic parameter variability in SiGe HBTs is also examined. Measurement results are compared with TCAD simulations to provide additional insights, and possible mitigation methods are discussed.

This paper provides insight into the transport mechanisms of the collector current in SiGe HBTs operating at cryogenic temperatures and compares three technology generations of devices. Based on the experimental data, a method to differentiate direct tunneling from quasi-ballistic transport is proposed. Measurements indicate that direct tunneling becomes more significant at cryogenic temperatures. The effects of technology scaling on the direct tunneling were investigated using TCAD. Direct tunneling was found to be sensitive to the base width and the Ge profile. It is predicted that without an increase in the Ge content, direct tunneling may dominate over quasi-ballistic transport at the limits of technology scaling.

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain ( $\beta$ ) at high injection, where circuits are typically biased to extract maximum device performance.

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding ${J}_{C,{\textsf {crit}}}$ and ${V}_{{\textsf {CB}},{\textsf {crit}}}$ across the ${J}_{C}$ – ${V}_{\textsf {CB}}$ plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology.

To support many power management applications in wireless sensor networks, a previously developed model is modified to predict the terminal behaviour of a supercapacitor under a dynamic charging/discharging power profile. In addition, a robust model parameter identification method based on the genetic algorithm is developed to determine the model parameters using a dynamic test and a self-discharge experiment. On the basis of the supercapacitor power input model, charge redistribution related figures of merit are derived and used to evaluate the significance of charge redistribution for supercapacitors with various rated capacitance. The results show that supercapacitors with different sizes share similar charge redistribution phenomenon. Furthermore, the charge redistribution significance is studied from several perspectives to provide guidelines for designing power management techniques that can achieve full potential of the energy stored in the supercapacitors.

We present the first measurement results of a highly scaled, 90-nm silicon–germanium heterojunction bipolar transistor (SiGe HBT) operating at cryogenic temperatures as low as 70 mK. The SiGe HBT exhibits a transistor-like behavior down to 70 mK, but below 40 K, the transconductance suggests the presence of non-equilibrium transport mechanisms. Despite the non-ideal base current at cryogenic temperatures, a $dc$ current gain $(\beta) > 1$ is achieved for $I_{C} > 1$ nA, suggesting that ultra-low-power low-noise amplifiers should be viable. Exposure of the SiGe HBT to strong magnetic fields (±14 T) is also presented to help understand the nature of the non-ideal current.

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.

In quantum computing, metrology, single-photon counting, and nanomechanics, weak electronic signals at extremely low temperatures need amplification. To this end, the authors build and study silicon-germanium heterojunction bipolar transistors, which offer excellent amplifier characteristics, integrability with silicon quantum electronics, low cost, and manufacturability. Their research at the junction of physics and electrical engineering is a step toward next-generation integrated circuits at the 90-nm scale for this temperature regime.