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A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) emerged as a boon to the industries due to the fact that it fulfils different industrial aspects such as reduced electromagnetic interference, lower maintenance, less installation area and reduced harmonic content. MLI generates a staircase output voltage with suitable combination of power devices and DC voltage sources. In this work, a generalized cascaded MLI is proposed that employs only a half-bridge converter rather than the full H-bridge converter for the polarity-reversal (on which the maximum DC link voltage appears) and thereby also reduces the required number of power switches. Five different types of algorithm in the proposed configuration have been studied and the most optimal algorithm is further elaborated and implemented. A specimen 7-level inverter of the proposed configuration is modeled in MATLAB/Simulink and is further implemented in the laboratory using the controller DS1103. The experimental results for different modulation indices are further amalgamated and verified with the simulation results. Nevertheless, a comparative assessment of different performance-related parameters of the proposed topology along with the generalized expressions is carried out and are also compared with some of the recently published MLI topologies. [ABSTRACT FROM AUTHOR]

Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper. [ABSTRACT FROM AUTHOR]

This study presents the performance analysis of a new asymmetrical multi‐level inverter using reduced number of switches for a single‐phase grid‐tied photovoltaic (PV) system. The solar PV panels of unequal power rating are connected in an appropriate manner to obtain the DC link voltages of suitable ratio for an asymmetrical cascaded multi‐level inverter. The PV power, voltages as well as the current injected into the grid have been controlled using the separate maximum power point tracking, voltage controllers and a current controlled technique to achieve the maximum power with sinusoidal current with a unity power factor. The variations of DC link voltages, inverter voltage and injected grid current are simulated and are experimentally verified under the variable irradiation as well as grid voltage fluctuation. The simulation and the corresponding hardware results of the proposed reduced switch asymmetrical seven‐level inverter for a low‐power residential grid‐tied PV system is also presented. [ABSTRACT FROM AUTHOR]

This study presents a generalised online switching scheme for a space vector pulse-width modulation (SVPWM)- based multilevel inverter of any voltage level. The proposed SVPWM algorithm implements a generalised three-(similar to five) and seven-segment switching scheme using the three most desired switching states and one suitable redundant state for each triangle. In addition, a novel three-segment and seven-segment switching scheme has been proposed, which eliminates extra switching commutations and hence minimises the switching frequency of the devices while reducing harmonics. The proposed modulation algorithm using the generalised expressions is implemented online. The performance of the proposed novel algorithm for N-level inverter is tested experimentally on a five-level cascaded inverter at various fundamental frequencies and the experimental results are verified with the simulation results. [ABSTRACT FROM AUTHOR]

This study presents a simple and a generalised space vector pulse-width modulation scheme for a neutral point clamped multi-level inverter as well as cascaded inverter of any level. This modulation algorithm implements the online generation of desired switching states and their sequences through generalised expressions without any predetermined stored data in a memory look-up table. The proposed algorithm also incorporates the concept of reference vector and on-time modification combined during the over-modulation region for any level of inverter. Performance of the proposed modulation algorithm is tested experimentally through a digital signal processor-based controller for a five-level cascaded inverter with very low execution time that does not depend much on the level of inverter. The simulation waveform and the harmonic analysis of the voltage at different modulation index are presented and these are verified with the experimental results. [ABSTRACT FROM AUTHOR]