Digital active gate driving has been shown to effectively manage the switching performance for power devices with the adjustable driving waveforms. However, most of the studies are based on a dedicated test circuit rather than a practical inverter with the sinusoidal output current. In fact, it is the dependency on the load current that makes the design of the gate driving profiles a critical issue. To investigate the digital active gate driver in an inverter application, this paper has applied optimal patterns adapting to time-varying output load current. Prior to the search of optimal patterns, the proper design framework is discussed with three frameworks of different time resolutions. With the proper resolution determined for patterns, multiple optimizations are carried out for different current conditions. In this way, the search for optimal patterns can be completed in an efficient time. Next, a look-up table of optimal switching pattern in correspondence with each certain load current condition was built in advance. According to the output load current, the optimal pattern is selected based on the look-up table. Compared to the conventional constant driving waveform, the power loss has been reduced by 7% with a full optimal look-up table applied.