Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla, Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits, Abadal Cavallé, Sergi, Sheinman, Benny, Katz, Oded, Markish, Ofer, Elad, Danny, Fournier, Yvan, Roca, Damian, Hanzich, Mauricio, Houzeaux, Guillaume, Nemirovsky, Mario, Alarcón Cot, Eduardo José, Cabellos Aparicio, Alberto, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla, Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits, Abadal Cavallé, Sergi, Sheinman, Benny, Katz, Oded, Markish, Ofer, Elad, Danny, Fournier, Yvan, Roca, Damian, Hanzich, Mauricio, Houzeaux, Guillaume, Nemirovsky, Mario, Alarcón Cot, Eduardo José, and Cabellos Aparicio, Alberto
Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in diverse computing domains, directly and indirectly leading to diminishing performance returns as the many-core era is approaching. Novel interconnect technologies could help revert this trend by offering, among others, improved broadcast support, even in large-scale chip multiprocessors. This article outlines the prospects of wireless on-chip communication technologies pointing toward low-latency (a few cycles) and energy-efficient broadcast (a few picojoules per bit). It also discusses the challenges and potential impact of adopting these technologies as key enablers of unconventional hardware architectures and algorithmic approaches, in the pathway of significantly improving the performance, energy efficiency, scalability, and programmability of many-core chips., Peer Reviewed, Postprint (author's final draft)